Unit 3

Serial Interfaces
Memory Subsystem
 Syllabus
Serial Interface Standards
SPI, I2C, Controller Area Network (CAN), Universal Serial
Bus(USB)
Memory Subsystem
Introduction, Classifying Memory, Memory Interface, ROM
Overview, Flash Memory, Static RAM Overview, Dynamic
RAM Overview, An SRAM Design, A DRAM Design,
DRAM Memory Interface, Memory Map
Reference Book
James K Peckol, Embedded Systems A contemporary
Design Tool, John Weily, 2008, ISBN: 0-444-51616-6
(Memory Subsystem)

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Serial Buses: I2C (Inter IC)
Originally, bus defined by Philips providing a simple way to talk
between ICs by using a minimum number of pins.
A set of specifications to build a simple universal bus
guaranteeing compatibility of parts (ICs) from different
manufacturers:
-Simple Hardware standards
-Simple Software protocol standard
No specific wiring or connectors -most often its just PCB
tracks.

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 I2C contd..
Has become a recognised standard throughout industry
and is used now by ALL major IC manufacturers.
Common devices capable of interfacing to an I2C bus
include EEPROMs, Flash and some RAM memory
devices , real time clocks, watch dog timers and
microcontrollers.

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I2C Features
Only two bus lines are required: a serial data line (SDA) and a
serial clock line (SCL).
Each device connected to the bus is software addressable by a
unique address and simple master/slave relationships exist at
all times; masters can operate as master-transmitters or as
master-receivers.
Its a true multi-master bus including collision detection and
arbitration to prevent data corruption if two or more masters
simultaneously initiate data transfer.

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 I2C features
Serial, 8-bit oriented, bi-directional data transfers can be
made at up to 100 kbit/s in the Standard-mode, up to
400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the
High-speed mode.
The number of ICs that can be connected to the same
bus segment is limited only by the maximum bus
capacitive loading of 400 pF.

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 I2C Hardware Characteristics

All connected devices have open collector ( Open drain) driver

stages that can transmit the data by pulling bus low.

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 I2C: Master- Slave Configuration

Master:
Initiates a transfer by generating start and stop conditions
Generates the clock
Transmits the slave address
Determines data transfer direction
Slave:
Responds only when addressed
Timing is controlled by the clock line
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 I2C :Multi-Master slave Mode

The I2C-bus is a multi-master bus. This means

that more than one device capable of controlling
the bus connected to it.
The arbitration logic gives of the bus to only
one device.
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 I2C:Start & Stop conditions
A transition of the data line while the clock line is high is
defined as either a start or a stop condition.
Both start and stop conditions are generated by the bus
master
The bus is considered busy after a start condition, until a
stop condition occurs

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 I2C: Bit transfer on bus
In normal data transfer, the data line only changes state when
the clock is low

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 I2C: Data transfer on I2C bus
Start Condition
Slave address + R/W
Slave acknowledges with ACK
All data bytes
Each followed by ACK
Stop Condition

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 I2C Addressing: 7 bit & 10 bit formats
The 1st byte after START determines the Slave to be
addressed( Generated by master).

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 Acknowledge
The acknowledge-related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse.
The receiver must pull down the SDA line during the acknowledge
clock pulse so that it remains stable LOW.
If a master-receiver is involved in a transfer, it must signal the end
of data to the slave- transmitter by not generating an acknowledge
on the last byte that was clocked out of the slave.
The slave-transmitter must release the data line to allow the
master to generate a STOP or repeated START condition.

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 I2C: Sequence operations
1. Master sends start condition (S) and controls the clock
signal
2. Master sends a unique 7-bit slave device address
3. Master sends read/write bit (R/W) 0 - slave receive, 1
- slave transmit
4. Receiver sends acknowledge bit (ACK)
5. Transmitter (slave or master) transmits 1 byte of data
6. Receiver issues an ACK bit for the byte received
7. Repeat 5 and 6 if more bytes need to be transmitted.
8. For write transaction (master transmitting), master
issues stop condition (P) after last byte of data.
9. For read transaction (master receiving), master does not
acknowledge final byte, just issues stop condition (P) to
tell the slave the transmission is done
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 Bus Arbitration
If there are two masters on the same bus, there are arbitration
procedures applied if both try to take control of the bus at the
same time.
When two chips try to start communication at the same time
they may even generate a few cycles of the clock and data that
match, but eventually one will output a low when the other
tries for a high. The low wins, so the loser device withdraws
and waits until the bus is freed again.
Once a master (e.g., microcontroller) has control, no other
master can take control until the first master sends a stop
condition and places the bus in an idle state.

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 Bus arbitration
The two MCU's are accessing a slave in write mode at address
1111001. The slave acknowledges this. So far, both masters are under
the impression that they "own" the bus.
MCU1 wants to transmit 01010101 to the slave, while MCU 2
wants to transmit 01100110 to the slave.
The moment the data bits do not match anymore one of them loses
arbitration and backs off.
For as long as there has been no STOP present on the bus, it won't
touch the bus and leave the SDA and SCL lines alone (yellow zone).

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 I2C of MSP430 MC

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 Questions
What is clock stretching?
What is bus arbitration?
How to extend the length of I2C bus?

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Serial Peripheral Interface(SPI)
Defined by Motorola.
It is a synchronous serial data link that operates in full duplex
A serial clock line synchronizes the shifting and sampling of the
information on two serial data lines.
The SPI is mainly used to allow a microcontrollers to
communicate with peripheral devices such as EEPROMs.
SPI devices communicate using a master-slave relationship.
Due to its lack of built-in device addressing, SPI requires more
effort and more hardware resources than I2C when more than
one slave is involved.
SPI tends to be simpler and more efficient than I2C in point-to-
point (single master, single slave) applications for the very same
reason; the lack of device addressing means less overhead.
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 SPI signals
Clock: SCLK
Master Data Output, Slave Data Input: MOSI
Master Data Input, Slave Data Output: MISO
Slave Select: SS
- Actually a 3 + n wire interface with n = number of
devices

Single master, single slave SPI implementation

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 Single master, multiple slave SPI implementation

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 Data transmission
Transmissions normally involve two shift registers of some given word
size (8 /16 bit) one in the master and one in the slave; they are
connected in a ring.
Data is usually shifted out with the most significant bit first, while
shifting a new least significant bit into the same register.
Transmissions may involve any number of clock cycles. When there is no
more data to be transmitted, the master stops toggling its clock.
Normally, it then deselects the slave.

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Clock polarity and phase
In addition to setting the clock frequency, the master must also configure the
clock polarity and phase with respect to the data.
E.g. S12x Freesacle Architecture Notations
At CPOL=0 the base value of the clock is zero
At CPOL=1 the base value of the clock is one
For CPHA=0, data is captured on the clock's rising edge and data is
propagated on a falling edge.
For CPHA=1, data is captured on the clock's falling edge and data is
propagated on a rising edge

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Controller Area Network(CAN)
CAN is a serial bus system used to communicate between several
embedded 8-bit and 16-bit microcontrollers.
It was originally designed for use in the automotive industry but is
used today in many other systems (e.g. home appliances and
industrial machines).
Highest Baud Rate is 1Mbit.
CAN uses a message oriented transmission protocol.
There are no defined addresses, just defined messages.

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 CAN: Automobile Example

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 Automobile Example: Connectivity

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Automobile Example: Connectivity with CAN

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 CAN : Nodes/ Stations

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CAN: Broadcast Communication
This means that all nodes can "hear" all transmissions. There is
no way to send a message to just a specific node; all nodes will
invariably pick up all traffic.
The CAN hardware, however, provides local filtering so that
each node may react only on the interesting messages.

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 Basic Configuration

Note: 80C166 & C167CR Infineon MCUs, 81C9x CAN Controller

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CAN bus overview
The physical layer uses differential transmission on a twisted
pair wire. The bus uses Non-Return To Zero (NRZ) with bit-
stuffing.
The nodes are connected to the bus in a wired-and fashion: if
just one node is driving the bus to a logical 0, then the whole
bus is in that state regardless of the number of nodes
transmitting a logical 1.
Max. transfer rate of 1Mbps at a maximum bus length of 40
meters or 130 feet when using a twisted wire pair which is the
most common bus medium used for CAN.
Message length is short with a maximum of 8 data bytes per
message and there is a low latency between transmission
request and start of transmission. The messages are protected
by a CRC type checksum
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 CAN bus overview
The bus access is handled via the advanced serial
communications protocol Carrier Sense Multiple
Access/Collision Detection with Non-Destructive
Arbitration. This means that collision of messages is avoided by
bitwise arbitration without loss of time.
There is no explicit address in the messages, instead, each
message carries a numeric value which controls its priority on
the bus, and may also serve as an identification of the contents
of the message.
An elaborate error handling scheme that results in
retransmitted messages when they are not properly received.
There are effective means for isolating faults and removing
faulty nodes from the bus.

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 Layered Structure of CAN

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CAN: Bit Encoding
Message Coding: NRZ(Non Return to Zero) Code
Fewer Transitions: less EMI (Difficult to extract clock: No oscillator
drift)

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 CAN: Bit Encoding
Bit stuffing is done to extract clock & reduce oscillator
drift requirements.

Stuffing is done for five consecutive zeros or ones.

( Source: Thomas Nolte, et.al., Using bit-stuffing distributions in CAN analysis,
IEEE Real-Time Embedded Systems Workshop, Dec. 3, 2001)

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 CAN bus Characteristics: Wired AND

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 CAN bus Characteristics: Wired AND(Contd..)

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 Bus Access and Arbitration CSMA /CD NDA
CSMA/CD NDA Carrier Sense Multiple Access/Collision
avoidance by Non Destructive arbitration

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 Bus Levels according to ISO-IS 11898
A recessive bit is represented by both CAN bus lines driven to a
level of about 2.5 V so that the differential voltage between
CAN_H and CAN_L is around 0V.
A dominant bit is represented by CAN_H going to about 3.5 V and
CAN_L going to about 1.5 V. This results in a differential voltage
for a dominant bit of about 2V.

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 CAN Protocol: Message Transfers
The message transfer is controlled by four different types of
frames.
Data Frame: Carries data from transmitter to receiver.
Remote Frame: Transmitted by a node to request for a transfer
frame with same identifier.
Error Frame:Transmitted by a node, on detecting a bus error.
Overload Frame: Used to provide a delay between two
successive data frames or remote frames.

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 CAN Messages
Data Frame & Remote Frame

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 CAN Protocol: Message Transfers
Data Frame Formats

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CAN Protocol: Data Frame
The Data Frame is the most common message type. It
comprises the following fields
Start of Frame: Marks the beginning of data frames &
remote frames.
The Arbitration Field, which determines the priority of the
message when two or more nodes are contending for the bus.
The Arbitration Field contains:
For CAN 2.0A, an 11-bit Identifier and one bit, the RTR bit, which is
dominant for data frames and Recessive for remote frame.
For CAN 2.0B, a 29-bit Identifier and the RTR bit.
Control Field, consists of six bits: Data Length Code(4 bits)
2 bits are reserved for future expansion.
The number of bytes in data field is indicated by data length
code.
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Data Frame
Data Field, which contains zero to eight bytes of data.
CRC Field, which contains a 15-bit checksum calculated on
most parts of the message. This checksum is used for error
detection.
ACK Field is 2 bits long contains the ACK SLOT and ACK
DELIMITER :
The transmitting station sends two recessive bits ACK field.
A receiver which has received data properly, reports sender
by sending dominant bit in ACK SLOT.

End of frame: Sequence of Seven recessive bits

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 Data Frame

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Remote Frame
The Remote Frame is just like the Data Frame, with
two important differences:
It is explicitly marked as a Remote Frame (the RTR bit in
the Arbitration Field is recessive)
There is no Data Field.
The intended purpose of the Remote Frame is to
request the transmission of the corresponding Data
Frame.
E.g.: If, say, node A transmits a Remote Frame with
the Arbitration Field set to 234, then node B, if
properly initialized, might respond with a Data Frame
with the Arbitration Field also set to 234.
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 Remote Frame

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 Error Handling
Different Errors
Bit error
E.g. Bit received is not that was transmitted (except in
arbitration and acknowledgement)
Bit Stuffing error
-More than 5 consecutive bits of equal polarity
CRC error
-Received CRC code does not match calculated code
Form error
E.g Violation of end frame (EOF) format, No dominant bits
allowed in: CRC Delimiter, ACK Delimiter.
ACK error
Transmitting node receives no dominant acknowledgement bit
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 Errors: Bit Error
Detected errors are made public to all other nodes via
Error Frames.
The transmission of the erroneous message is aborted
and the frame is repeated as soon as possible.

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 Errors: CRC Error
If node B detects a mismatch between the calculated and
the received CRC sequence , then a CRC error has
occurred.
Node B discards the message and transmits an Error
Frame to request retransmission of the garbled frame.

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Error States of CAN Nodes/Controller
A CAN controller can be in one of three states
Error active - the normal operating mode for a controller. Messages
can be received and transmitted. On detecting an error an active
error flag is sent.

Error passive - a mode entered when the controller has frequent

problems transmitting or receiving messages. Messages can be
received and transmitted. On detecting an error while receiving, a
passive error flag is sent.

Bus off - entered if the controller has serious problems with

transmitting messages. No messages can be received or transmitted
until the CAN controller is reset by the host microcontroller or
processor.

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 Error States
The mode of the controller is controlled by two error counters
- the Transmit Error Counter(TEC) and the Receive Error
Counter (REC).
Error states are shown in diagram below.

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 Error Frames
An Error Frame is generated by any node that detects a bus error.
The Error Frame consists of 2 fields, an Error Flag field followed
by an Error Delimiter field. The Error Delimiter consists of 8
recessive bits and allows the bus nodes to restart bus
communications cleanly after an error.

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 Error Frame: Error Flags
When an error is detected by a node, it sends an error flag on the bus.
If an error-active node detects a bus error then the node
interrupts transmission of the current message by generating an
active error flag.
The active error flag is composed of six consecutive dominant bits.
This bit sequence actively violates the bit stuffing rule.
All other stations recognize the resulting bit stuffing error and in turn
generate Error Frames themselves. The Error Flag field therefore
consists of between six and twelve consecutive dominant bits
(generated by one or more nodes).
The Error Delimiter field completes the Error Frame.
After completion of the Error Frame bus activity returns to normal
and the interrupted node attempts to resent the aborted message.

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 Error Frame: Error Flags
If an error passive node detects a bus error then the node
transmits an passive Error Flag followed, again, by the
Error Delimiter field.
The passive Error Flag consists of six consecutive recessive
bits, and therefore the Error Frame (for an error passive
node) consists of 14 recessive bits (i.e. no dominant bits).
From this it follows that, unless the bus error is detected by
the node that is actually transmitting (i.e. is the bus master),
the transmission of an Error Frame by an error passive
node will not affect any other node on the network.
If the bus master node generates an error passive flag then
this may cause other nodes to generate error frames due to
the resulting bit stuffing violation.
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 Physical Layer
Bus wires twisted pair, 120R termination at each end.
2 wires driven with differential signal(CAN_H,CAN_L)
But also an optical medium would be possible for CAN. In this
case, the recessive state would be represented by the signal
light off , the dominant state by the signal light on.

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 CAN bus connectors according to CiA-DS 102-1

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Questions
CAN is Synchronous or Asynchronous?
Write C-program to form data frame of CAN bus?
Write C-program to handle errors using CRC?

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USB(Universal Serial Bus):Introduction
The USB is a asynchronous, Half Duplex, Packet based serial
data bus designed to carry relatively large amounts of data over
relatively short cables with differential signalling.
The USB is an addressable bus system, with a seven-bit address
code so it can support up to 127 different devices or nodes at
once (the all zeroes code is not a valid address).
Hot pluggable/Automatic configuration/Hot Swapping
Devices can be plugged into and unplugged from the bus
without having to turn the power off and on again, re-boot the PC
or even manually start a driver program.
Loss less data transfers.

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 Introduction.
Speed (Theoretical)
USB 1.1 Up to 12 Mbps
USB 2.0 Up to 480 Mbps
USB 3.0 Up to 5 Gbps
No power supply required: (Not Self Powered)
-Devices can pull up to 500 mA from the bus in USB 2.0 &
upto 900 mA in USB 3.0 (Active mode).
Direction-all transactions are directed with respect to the
host. IN transactions send data from the peripheral to the
host. OUT transactions send data from the host to the
peripheral.

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USB : Terminology
Host computer that controls the interface
Hub device with one or more connections to USB devices
plus hardware to enable communications with each device
Device something that attaches to a USB port
Port a connector on the USB Host bus
Suspend Device enters Suspend after 3mS of inactivity on
the bus to minimize power consumption. Host uses timing packet
to keep Peripherals active.
Enumeration Initialization sequence to inform the host what
device was attached to the bus. Device parameters are conveyed
at this point.

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USB: Implementation
Host to a device requires interaction between a number of layers
and entities.

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USB: Layers
The USB Bus Interface layer provides physical/signaling/packet
connectivity between the host and a device.
The USB Device Layer is the view the USB System Software, has for
performing generic USB operations with a device.
The Function Layer provides additional capabilities to the host via an
appropriate matched client software layer.
Client Software: Software that executes on the host, corresponding
to a USB device. This client software is typically supplied with the
operating system or provided along with the USB device.
The USB System Software is typically supplied with the operating
system, independently of particular USB devices or client software.

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 USB: Connections

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 USB Communication Flow
Figure illustrates how communication flows are carried over
pipes between endpoints and host side memory buffers.

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 USB Communication Flow
A USB logical device appears to the USB system as a
collection of endpoints.
Associations between the host software and a USB
device endpoint are called pipes
Client software manages an interface using pipe
bundles (associated with an endpoint set).
Client software requests that data be moved across the
USB between a buffer on the host and an endpoint on
the USB device.

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 Device Endpoints
An endpoint is a uniquely identifiable portion of a USB device
that is the terminus of a communication flow between the host
and device.
Each USB logical device is composed of a collection of
independent endpoints.
Each endpoint on a device is given at design time a unique
device-determined identifier called the endpoint number.
Endpoint Zero:The endpoints with endpoint number zero are
always accessible once a device is attached, powered, and has
received a bus reset.(Gives device configuration information)

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 USB: Connectors Pin Assignment

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 Attach Event
Plugging in a USB device to the host root hub or external hub is
considered an attach event. The device has a 1.5 K pull-up resistor
to the USB supply (VBUS).
Pull-up to D+ signals a full speed device. D- is for low speed devices.
On attach event, enumeration begins.

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Differential Signaling
Signaling levels
Differential 1 (D+) -(D-) > 200mV
Differential 0 (D+) (D-) < -200 mV
On disconnect, D+, D- become same voltage value .
Condition is known as a Single-Ended 0.
On connection of a high-speed device, D+ > D-. Idle
state is D+ > D-, so idle state is a differential 1.
On connection of a low-speed device, D- > D+. Idle
state is D- > D+, so idle state is a differential 0.

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USB: Bit Encoding
NRZI(Inverted) is followed.

0 -Transition, 1- No Transition
Bit stuffing is done to avoid long runs of 1s.

Note:
Actually NRZI- 0 No Transition, 1- Transition
Reversed in USB.
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Transactions
A transaction is transfer of data between host and USB device
(function) - either Host to Function (OUT) or Function to Host
(IN)
Data sent in packets
For IN transaction: Host transmits IN packet
Function responds with data packet, or with NAK packet
if cant return data, or with STALL packet if permanently
stalled.
If host receives valid DATA packet, then host returns an ACK
packet to complete transaction.
OUT transaction is handled similarly.
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Packets
Packetsblock of information with a defined data structure.
Different Packet Formats

(Bytes)

All packets starts with Start of Packet Sync Pattern ( 8 bits, 7 zeros + 1
one) and ends with End of Packet bit (differential Zero).
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Packets
The token packet would be used to identify the
transfer.(Only Host can issue) E.g. setup, IN, OUT.
The SOF packet is sent on the frame boundaries to
provide timing and frame counts.
Data packet is the payload.
Handshake packets provide for communication
robustness to verify that the data was
receive/transmitted properly. E.g. ACK,NAK

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Packet Identifiers(PID)
PIDs indicates transaction type and has different meaning
based on the transaction. Lower nibble is the inversion of the
upper nibble provided for error checking.

IN data transfers to the host

OUT data transfers from the host
SOF Timing marker at 1mS
Setup Specifies control transfers
Data0 Data packet PID even
Data1 Data packet PID odd
ACK data received without error
NAK Device busy or no data available
Stall Unsupported control request.

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USB data transfer types
The USB architecture supports four basic types of data transfers:
Control Transfers
Control data is used by the USB System Software to configure
devices when they are first attached.
Bulk Transfers
Bulk data typically consists of larger amounts of data, such as that
used for printers or scanners.
Interrupt Transfers
A small, limited-latency transfer to or from a device is referred
to as interrupt data.
Such data may be presented for transfer by a device at any time and
is delivered by the USB at a rate no slower than is specified by the
device.
An example of interrupt data is the coordinates from a pointing
81 device
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 Data transfers
Isochronous Transfers
Isochronous data is continuous and real-time in creation,
delivery and consumption.
Isochronous data must be delivered at the rate received to
maintain its timing.
Isochronous data is sensitive to delivery delays.
A typical example of isochronous data is voice.

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Data Transfers: Example

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 Bulk Transactions: Data Flow
Bulk transactions use a three-phase transaction consisting of
token, data, and handshake packets as shown in figure.

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 Isochronous Transactions: Data Flow
Isochronous (ISO) transactions have a token and data phase, but no
handshake phase.
The host issues either an IN or an OUT token followed by the data
phase in which the endpoint (for INs) or the host (for OUTs)
transmits data.
Guaranteed delivery time of packets for data streaming.

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 USB: Device Sates
Idle state
All drivers are off.
Suspend state
Low power state with < 500 uA current consumption requirement
in USB 2.0.
Timeout
After 3 mS of inactivity on the bus all devices are required to
enter the Suspend state
SOF marker devices keep devices out of suspend
Global suspend when host goes into standby
Selective suspend
Host can issue request to put a specific device into suspend
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Memory Subsystem
Classifying Memory
RAM-Random Access Memory
-Any location in memory is visible for immediate access rather than having
to sequence through predecessor locations.
-The times for a read operation and a write operation are comparable.
- It may organized as bytes or words.
Static RAM(SRAM)
-A more complex memory cell design with bit storage implemented
using latch type mechanism.
- I/O is asynchronous with respect to any external system clocks
SRAM used for on-chip memory like caches and scratchpads.

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 Dynamic RAM (DRAM)
- A simple memory cell design with bit storage implemented using a
stored charge mechanism.
-The stored charge can leak away if it is not repeatedly restored.
- I/O is asynchronous with respect to any external system clocks
-DRAM is off-chip and Slower than SRAM
Synchronous DRAM
- SDRAM synchronizes all addresses, data and control signals to
the system clock.
- Allows much higher data transfer rates than asynchronous
transfers.

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 Memory .
DDR(Double Date Rate) SDRAM
- DDR memorys primary advantage is the ability to fetch data on
both the rising and falling edge of a clock cycle, doubling the data
rate for a given clock frequency.
-DDR1, DDR2,DDR3 are different speed (data transfer rate)
variants.
Flash Memory
-Type of ROM.
- It can be programmed in site(In System Programming)
-Flash memory works much faster than traditional EEPROMs
because instead of erasing one byte at a time, it erases a block
or the entire chip, and then rewrites it.
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 Memory Hierarchy
Smaller, L0:
faster, registers CPU registers hold words retrieved from
and L1 cache.
costlier L1: on-chip L1
(per byte) cache (SRAM) L1 cache holds cache lines retrieved
storage from the L2 cache memory.
On /Off Chip L2
devices L2: off-chip L2
cache (SRAM) L2 cache holds cache lines
retrieved from main memory.

L3: main memory

(DRAM)
Larger, Main memory holds disk
slower, blocks retrieved from local
disks.
and
cheaper L4: local secondary storage
(per byte) (local disks)
Local disks hold files
storage retrieved from disks on
devices remote network servers.

L5: remote secondary storage

(distributed file systems, Web servers)
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 Memory hierarchy..

L2 Cache

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 General memory Interface
Memory=Array System
Read Access: Read Operation
Write Access: Write Operation

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Memory Interface
Generally memory interface requires 3 types of signals.
address, data & Control .

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Access time n Cycle time

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 Terminology
Block Size
The units of data transfer between hard disk & main memory
are called blocks.
The block size specifies the number of words each block.

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 Terminology..
Memory Bandwidth
It is a measure of the word transmission rate to and from
memory .
Specified in units of frequency or bits/second
Page
The units of data transfer between main memory & cache
are called page.

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ROM Overview
The ROM is generally viewed as a read only device( during
execution).
The transistors are used to connect to ground bit inside a memory
word (a floating connection is read as logic 1).

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ROM: Read Operation
A value is read from a ROM by asserting one of the row
lines.

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 SRAM
The high level interface to SRAM is very similar to that for
the ROM.
The major difference arise from support for write capability
(during execution).

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 SRAM: Timing diagrams
CS

OE

Address
R/W

Data

CS

OE

Address
R/W

Data
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Memory Map

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 Memory Map: Example 1
Interface two 4k x 8 EPROMS and two 4k x 8 RAM chips to
8086. Select suitable maps.
Solution:
- After reset, the IP & CS is initialized to 0000h & FFFFH
to form physical address FFFF0H
- This address must lie in EPROM (Program Memory)
- RAM (data memory) address can be selected any where in
1Mb of memory(Except the locations allocated for
EPROM)

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 Question 1..
Odd & Even Banks

8 K bytes
No address lines =13: (213= 8K)

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 Question 1..
Memory Map generation

RAM & ROM chip size :4 K bytes

No of address lines :12 (A12-A1)
A0 is used to select Even bank
ROM address map should include RESET address

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 Question 1..
Memory Map

A0 is chip select signal for even bank.

A1-A12 Address lines
A13-A19 Chip Select signal for RAM & ROM

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 Memory Map: Example 2
Design an interface between 8086 CPU and two chips of 16 x 8
EPROM and two chips of 32k x 8 RAM. Select the starting address
of EPROM suitably. The RAM address must start at 00000H.
Solution:
No. of address lines ROM: 15 (215= 32k x 8)
No. of address lines RAM : 16(216=64k x 8)
Reset address:FFFF0H
Memory Map:

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 Question 1
The memory map shown in previous examples is Von
Neumann or Harvard?

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 Interfacing Devices: 8282 Latch
This is D- latch with 3 state output buffers.
STB=1, latches the bit applied to input data lines.
OE=0 ,enables output lathes
OE=1, Forces output to high
impedance state.

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 8286 octal bus transceiver
OE is to enable data transmission.
T is used control
direction

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 Latches:
Demultiplexing
address & data
bus

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Transceiver

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 8086:Write Cycle- Bus timings

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 8086: Read cycle-Bus timings

A19 S7 S3

D15 D0 D15 D0

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