IMPLEMENTATION

OF DIGITAL
CIRCUIT USING
VHDL
By: Avinash Sanapala
What is VHDL ?

The VHDL acronym stands for:

VHSIC
Hardware
Description
Language

It is a hardware description language used in Electronic Design Automation to describe digital

and mixed-signal systems such as field-programmable gate arrays (FPGA) and integrated circuits (IC).
The basic body of a VHDL program consists of :
The Entity unit in the VHDL file describes the Interface of the device.
The Architecture unit in VHDL file describes the Body of the device.
The Components unit in VHDL file is used to Instantiate a module.
Design implemented by using VHDL.
Components

There are 4 different components that are used in the given design are :
3 bit Synchronous Counter
Sequence Detector of 101(using FSM)
Full Adder
2 Half Adder
The device :
The device interacts with the environment by 4 ports.
Clock,reset,Din,Dout.
Internal Structure
3 bit Synchronous Counter
Clock and reset are inputs.
Temp_seg (3 bit) is the output.

Sequence Detector of 101 using FSM

Din ,reset and clock are the inputs.
dout is the output .

Full adder is implemented by using 2 half adders

The output from the 3 bit synchronous counter is the input.
Sum and carry are the outputs .
Full Adder
Full adder is implemented by using 2 Half adder modules.
Half adder is defined as :

Instantiate the Half adder in Full adder

3 bit synchronous counter
It is having all flip-flops clocked simultaneously so that the outputs change simultaneously with
each other .
Entity :

Architecture :
 Sequence detector of 101 using FSM
Fsm is a mathematical model of computation. It is an abstract machine that can be in
exactly one of a finite number of states at any given time. Designed this Fsm using
Moore Machine. The number of states used in detecting this pattern are 4.
The architecture is defined as :
Top Module
Instantiate all the 3 components in the Top and map the internal signals respectively
:
Verification of the Design.
The testbench is a VHDL code that plays the role of a complete simulation environment.
The entity of a testbench does not have any ports because the testbench is the highest hierarchy
level in the test environment.
The instantiation of DUT in Tb :

Clock Generation

This would generate a clock of frequency of 1mhz

Test cases
1st test case
 2ND test case
 3rd test case
 4th test case
THANK YOU