Professional Documents
Culture Documents
Digital IC
Design
CHAPTER #3
PHYSICAL DESIGN
Stick Diagrams
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
3
STICK DIAGRAMS
VDD
VDD
x f ? x x’
GND
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
4
STICK DIAGRAMS
VDD
VDD
x x’
x f
GND
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
5
STICK DIAGRAMS
VLSI design aims to translate circuit concepts onto silicon.
Stick diagrams convey layer information through colour codes (or monochrome
encoding).
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
6
STICK DIAGRAMS
Does show all components/vias.
– Via is used to connect higher level metals from metal connection
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
7
STICK DIAGRAMS
Does not show
– Exact placement of components
– Transistor sizes
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
8
STICK DIAGRAMS
CMOS PROCESS LAYERS
Metal 4
Metal 3
Metal 2
Metal 1
n+ (n-diff)
p+ (p-diff)
polysilicon
contact
via
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
9
STICK DIAGRAMS
SOME RULES
Rule 1.
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
10
STICK DIAGRAMS
SOME RULES
Rule 2.
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
11
STICK DIAGRAMS
SOME RULES
Rule 3.
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
12
STICK DIAGRAMS
SOME RULES
Rule 4.
In CMOS a demarcation line is drawn
to avoid touching of p-diff with
n-diff. All pMOS must lie on one
side of the line and all nMOS will
have to be on the other side.
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
13
STICK DIAGRAMS
SOME RULES
Rule 5.
Metal 1 should be part of the contact.
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
14
STICK DIAGRAMS
Series and Parallel Connections
A B
A B
n+ n+ n+ n+ n+ n+
A B
A B
x x
n+ n+ n+ n+ n+ n+
y y
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
15
STICK DIAGRAMS
CMOS Inverters
VDD VDD
GND GND
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
16
STICK DIAGRAMS
CMOS NAND
VDD VDD
P1 P2
f
x1 N1 x1
F
x2 N2 x2
x1
x2 f
GND
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
17
STICK DIAGRAMS
CMOS AND
VDD VDD
P1 P2 P3
f
x1 N2 N1 x1
F
x2 N3 x2
x1
x2 f
GND
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
18
STICK DIAGRAMS
CMOS NOR
VDD VDD
x1 P1
x2 P2 x1
f F
N2 N1 x2
x1
x2 f
GND
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
19
STICK DIAGRAMS
CMOS OR
VDD VDD
x1 P1
x2 P2 P3 x1
f F
N2 N1 N3 x2
x1
x2 f
GND
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
20
STICK DIAGRAMS
Complex Circuits
F = A’+(B’+C’)D’
CD
VDD
A B C D F AB 00 01 11 10 VDD
0 0 0 0 1 00 1 1 1 1 C B A
0 0 0 1 1 01 1 1 1 1 B C
0 0 1 0 1 11 1 0 0 0
A
D
0 0 1 1 1 10 1 0 0 1
0 1 0 0 1 D
0 1 0 1 1 F = A’+C’D’+B’D’
F
0 1 1 0 1
0 1 1 1 1 F’ = AD+ABC
1 0 0 0 1
A
F
1 0 0 1 0
1 0 1 0 1
D
1 0 1 1 0 B
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0 C
1 1 1 1 0
GND
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
21
STICK DIAGRAMS
Complex Circuits
F = ((A+B+C)D)’
CD
VDD
A B C D F AB 00 01 11 10 VDD
0 0 0 0 1 00 1 1 0 1 A B C D
0 0 0 1 1 01 1 0 0 1 A
0 0 1 0 1 11 1 0 0 1
0 0 1 1 0 10 1 0 0 1
0 1 0 0 1 B D
0 1 0 1 0 F = D’+A’B’C’
0 1 1 0 1 F’ = BD + AD + CD F
0 1 1 1 0 C
= D(A+B+C)
1 0 0 0 1
F
1 0 0 1 0
1 0 1 0 1
D
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
A B C
1 1 1 1 0
GND
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
22
STICK DIAGRAMS
CMOS XOR
VDD
VDD VDD
A
A B OUT B
F
GND
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n
23
THANK YOU!
Any Question?
0 9 / 0 1 / 2 0 1 8 D i g i t a l I C D e s i g n