Introduction to

Push-Pull and Cascaded

Power Converter
Topologies
Presented by Bob Bell

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 About the Presenter

The author, Bob Bell, has been

involved in the power conversion
industry for 20 years, currently a
Principal Applications Engineer for
the National Semiconductor
Phoenix Design Center. The
Phoenix Design Center is
developing next generation power
conversion solutions for the
telecommunications market.

Education: BSEE Fairleigh

Dickinson University, Teaneck, NJ
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© 2003 National Semiconductor Corporation
Outline:
Buck Regulator Family Lines
Push-Pull Topology Introduction
Push-Pull Controller
Cascaded Push-Pull Topologies
Cascaded Controller
Cascaded Half-Bridge Topology Introduction

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 Common One-Switch Power
Converter Topologies
L
Vi n Vo
Vi n Vo

Buck Converter Boost Converter

L
Vi n
Vi n
Np Ns Vo Np Ns Vo

Na ux
Forward Converter Flyback Converter

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© 2003 National Semiconductor Corporation
 Common Two-Switch Power
Converter Topologies
Vin

L
L
Np Ns Vo
Ns Vo
Vin
Np
Np Ns
Ns

Half Bridge Converter

Push-Pull Converter

Vin
L

Ns Vo
Np

Ns

Full Bridge Converter 5

© 2003 National Semiconductor Corporation
 Buck Regulator Basics
VIN

IL

D*Ts

Ts
Q1
I(Q1)

VOUT
L1
D1
C1
I(D1)
VOUT = D * VIN

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© 2003 National Semiconductor Corporation
 Buck Converter
Characteristics
• Non-Isolated Grounds
• Voltage Step-down Only
• Single Output Only
• Very High Efficiency
• Low Output Ripple Current
• High Input Ripple Current
• High Side (Isolated) Gate Drive Required
• Large Achievable Duty Cycle Range
• Wide Regulation Range (due to above)
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© 2003 National Semiconductor Corporation
 Forward Converter
D1 L1
+
Vout

+
Np Nr Ns D2 C1 R

Vin
-
Vout = Vin x D x Ns
D3

Q1 I(L1) Np

1 2 3 4
Same transfer function as a
I(D1) =
Buck converter with an
I(Q1) x Np/Ns added turns ratio term

1 2 3 4
I(D2)
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1 2 3 4 © 2003 National Semiconductor Corporation

 Forward Diode Currents

Forward Diode D1
Current

Freewheel
Diode D2
Current

Vin =48V
Vout =3.3V
Iout = 5A
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© 2003 National Semiconductor Corporation
 Forward Converter
Characteristics
• A Forward Converter is a Buck type converter
with an added isolation transformer
• Grounds are isolated
• Voltage Step-down or Step-up
• Multiple Outputs Possible
• Low Output Ripple Current
• High Input Ripple Current
• Simple Gate Drive
• Limited Achievable Duty Cycle Range

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© 2003 National Semiconductor Corporation
 Push-Pull Topology
D1 L
+
Vout
+
np ns C R

np ns

Vg D2
Vin

Q2 Q1

PUSH PULL

Q1 Vout = Vin x D x Ns x 2
Q2 Np
D
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© 2003 National Semiconductor Corporation
 Push-Pull Switching Waveforms

Vin = 48V
Output Vout =3.3V
Inductor
Current I(L1)
Iout = 5A

Push Primary
Switch VDS(Q1)

Pull Primary
Switch VDS(Q2)

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© 2003 National Semiconductor Corporation
 Push-Pull Diode Currents

Vin = 48V
Vout =3.3V
Output Diode
Current I(D1)
Iout = 5A

Output Diode
Current I(D2)

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© 2003 National Semiconductor Corporation
 Core Utilization: Forward &
Push-Pull Converters
FLUX DENSITY FLUX DENSITY
B (GAUSS) B (GAUSS)

BSAT BSAT
Operation in Operation in
Quadrant 1 only Quadrants 1 & 3

BR

MAGNETIC FIELD
MAGNETIC FIELD INTENSITY
INTENSITY H (OERSTED)
H (OERSTED)

Forward Converter Push-Pull Converter

B-H Operating Area B-H Operating Area
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© 2003 National Semiconductor Corporation
 Push-Pull Characteristics

• A Push-Pull Converter is a Buck type converter with a

dual drive winding isolation transformer
• Push-Pull transformers and filters are much smaller than
standard Forward converter filters
• Voltage Stress of the Primary Switches is: Vin *2
• Voltage Step-down or Step-up
• Multiple Outputs Possible
• Low Output Ripple Current
• Lower Input Ripple Current
• Simple Gate Drive (dual)
• Large Achievable Duty Cycle Range

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© 2003 National Semiconductor Corporation
 LM5030 Push-Pull Controller
Vin ENABLE 7.7V REG Vcc

Features CLK

OSC Vcc
• Internal 15-100V start-up regulator Rt / SYNC

• CM control, internal slope comp. J OUT1

• Set frequency with single resistor 45uA K

S Vcc
– 100k – 600kHz 5V
0 SLOPECOMP
RAMP R
• Synchronizable Oscillator
COMP GENERATOR
OUT2
5K
• Error amp
1.25V PWM
100K
VFB
• Precision 1.25V reference
RTN
1.4V LOGIC
50K
• Programmable soft-start SS

• Dual mode over-current protection

• Direct opto-coupler interface CS
2K

• Integrated 1.5A gate drivers 0.5V

• Fixed output driver deadtime 0.625V

• Thermal shutdown CLK

Packages: MSOP10, SS 10uA

LLP10 (4mm x 4mm) SS / SD

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0.45V SHUTDOWN
COMPARATOR
© 2003 National Semiconductor Corporation
 LM5030 Push-Pull Demo Board

Performance:
Input Range: 36 to 75V
Output Voltage: 3.3V
Output Current: 0 to 10A
Board Size: 2.3 x 2.3 x 0.45
Load Regulation: 1%
Line Regulation: 0.1%
Current Limit

Measured Efficiency: 84.5% @ 5A

82.5% @10A
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© 2003 National Semiconductor Corporation
 LM5030 Push-Pull Demo Board
36V-75Vin to +3.3V @ 10A
Input:
36 – 75V

Output:
3.3V @ 10A

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© 2003 National Semiconductor Corporation
 LM5030 3G Base Station
RF Power Supply

Performance:
Input Range: 36 to 75V
Output Voltage: 27V
Output Current: 0 to 30A
Board Size: 6 x 4 x 2
Load Regulation: 1%
Line Regulation: 0.1%
Line UVLO, Current Limit
Output OV Protection

Measured Efficiency: 91% @ 30A (810W)

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© 2003 National Semiconductor Corporation
LM5030 3G Base Station RF Supply
-48Vin to +27V @ 30A

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© 2003 National Semiconductor Corporation
 Cascaded Buck & Push-Pull
Power Converter (Voltage Fed)
Buck Push-Pull
Stage Stage
N : N : 1 : 1
Vin Vpp Vout

BUCK
PUSH
CONTROL

CONTROLLER OSCILLATOR

FEEDBACK PULL

Buck Control Output is
pulse-width modulated to
regulate Vout
Push-Pull Outputs operate
continuously, alternating at
50% duty cycle
Buck Stage: Vpp = Vin * D
Push-Pull Stage: Vout = Vpp / N
Overall: Vout = Vin x D/N
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© 2003 National Semiconductor Corporation
 Cascaded Voltage-Fed
Converter Benefits
• A Voltage-Fed Push-Pull Converter is a Buck type
converter consisting of a Buck Regulation stage
followed by (cascaded by) a Push-Pull Isolation
Stage
• The Push-Pull Stage FET voltage stresses are
reduced to Vout x N x 2 over all line conditions
• The output rectification can be easily optimized due
to reduced and fixed voltage stresses
• The output rectification is further optimized since the
power is equally shared between the rectifiers over
all load and line conditions
• Favorable topology for wide input ranges

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© 2003 National Semiconductor Corporation
 Current Fed Push-Pull Concept
OUTPUT INDUCTOR REMOVED
Buck Stage Push-Pull Stage
33 - 76V Vout

Vcc
Vcc HB

Vin HI HO
HD
HS BUCK OUT CAP
REMOVED
LI LO
LD

LM5101
LM5041 Vss

PUSH

FEEDBACK
PULL
FB

• Push and Pull outputs operate continuously, alternating with a slight overlap.
• Output voltage is controlled by the Buck stage which operates at 2X the Push-Pull frequency.
• Continuous output current from the Push-Pull stage requires minimal filtering.
• High Efficiency achieved with low Push-Pull switching losses and matched Sync rectifier loading

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© 2003 National Semiconductor Corporation
 Cascaded Current-Fed
Converter Benefits
• A Current-Fed Push-Pull Converter is a Buck
type converter consisting of a Buck Regulation
stage followed by (cascaded by) a Push-Pull
Isolation Stage
• There is no high current output inductor!
• Reduced switching loss in Push-Pull stage
• Favorable topology for multiple outputs since all
outputs are tightly coupled
• Favorable topology for wide input ranges, since
the Buck stage pre-regulates while the Push-Pull
and Secondary operate independently of the
input voltage level

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© 2003 National Semiconductor Corporation
 Current-Fed Switching Voltages
Trace 1:
Push_Pull SWPUSHVDS
Vin = 60V
Trace 2: Vout =2.5V
Push_Pull SWPULL VDS Iout = 20A

Trace 3:
Buck Stage Switching
Node

Note: There is an overlap

time where both the Push
and the Pull switches
are ON.
This is required to
maintain the inductor
current path.

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© 2003 National Semiconductor Corporation
 Current-Fed Push-Pull Switches

Ch 1,2
Push-Pull VDS

Ch 3,4
Push-Pull IDS

Vin = 48V
Vout =2.5V
Iout = 20A

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© 2003 National Semiconductor Corporation
 Current-Fed Switch Waveforms
Expanded Scale
Ch 1,2
Push-Pull VDS

Ch 3,4
Push-Pull IDS

Note: Each switch carries

½ the current,
during the overlap time

Vin = 48V
Vout =2.5V
Iout = 20A

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© 2003 National Semiconductor Corporation
 Why is it important to reduce
secondary rectification losses?
Control
10%
Secondary
Transformer Rectifiers
20% 40%

Filter Inductor
15% Primary
Switching
15%
Estimate for typical 3.3V Output, 35 – 80V Input
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© 2003 National Semiconductor Corporation
 Comparison of Rectifier
Stresses

Example:
3.3V Out, 35 - 80V
Topology Rectifier Voltage Stresses Input Example: Assumptions
Forward Vin * (Ns/Np) 20V High Line with XFR Ratio 4:1
Push-Pull Vin * (Ns/Np) * 2 26.7V High Line with XFR Ratio 6:1
Cascaded PP Vout * 2 6.6V All Line conditions XFR Ratio 6:1

Example:
3.3V Out, 35 - 80V
Topology Rectifier Current Ratios Input Example: Assumptions
Forward Iout * D and Iout * (1-D) 16 / 84% Ratio at High Line
Push-Pull 50% * Iout 50% All line conditions
Cascaded PP 50% * Iout 50% All line conditions

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© 2003 National Semiconductor Corporation
 Sync Rectifier Waveforms

Ch 1
Sync1 VDS

Ch 2
Sync2 VDS

Vin = 48V
Vout =2.5V
Iout = 20A

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© 2003 National Semiconductor Corporation
 LM5041 Cascaded PWM
Controller
Features:
• Internal 100V Capable Start-up Bias Regulator
• Programmable Line Under Voltage Lockout with
Adjustable Hysteresis
• Current Mode Control
• Internal Error Amplifier with Reference
• Dual Mode Over-Current Protection
• Internal Push-Pull Gate Drivers with Programmable
Overlap or Deadtime
• Programmable Soft-Start
• Programmable Oscillator with Sync Capability
• Precision Reference
• Thermal Shutdown (165C)
Packages: TSSOP16 and LLP16 (5 x 5 mm)

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© 2003 National Semiconductor Corporation
 LM5041 Block Diagram
ENABLE Vcc
Vin 9V REG
UVLO

2.5V Vcc Vref

5V REF
UVLO
LOGIC
45uA UVLO
HYSTERESIS
0 (20uA)
SLOPECOMP
RAMP OFF TIME
5V
COMP GENERATOR GENERATOR
LM5041-1 ONLY
0.75V 5K CLK
PWM
100K HD
FB
1.4V
50K LD
LOGIC
SS S Q

CS
2K 0.5V
R Q Vcc

CLK + LEB 0.6V OSC PUSH

DRIVER

SS 10uA CLK
DEADTIME
SS DIVIDE OR
OSCILLATOR Vcc
BY 2 OVERLAP
CONTROL

ENABLE
PULL
DRIVER
0.45V
SHUTDOWN
Rt / SYNC TIME 32
COMPARATOR
© 2003 National Semiconductor Corporation
 LM5041 Current Fed Push-Pull
Demo Board

Performance:
Input Range: 36 to 75V
Output Voltage: 2.5V
Output Current: 0 to 50A
Board Size: 2.3 x 3.0 x 0.5
Load Regulation: 1%
Line Regulation: 0.1%
Line UVLO, Current Limit

Measured Efficiency: 89% @ 50A

91% @20A
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© 2003 National Semiconductor Corporation
LM5041 / LM5100 Demo Board
2.5V @ 50A Cascaded DC-DC Converter

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© 2003 National Semiconductor Corporation
 Cascaded Half-Bridge
Concept
Half-Bridge Vout
Stage

T1
Buck
Stage
Vin L1
33 - 76V
VDD
VDD
Vcc
Vin HD T1

LD
LM5100
LM5102
LM5041

PUSH

PULL
FB
FEED
BACK
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© 2003 National Semiconductor Corporation
 Cascaded Half-Bridge
Characteristics
• A Cascaded Half-Bridge Converter is a Buck type
converter consisting of a Buck Regulation stage
followed by (cascaded by) a Half-Bridge Isolation
Stage.
• The isolation stage is Voltage-Fed.
• Voltage splitter capacitors and a small output stage
inductor are required.
• Dead time is required for Half-Bridge switches
• The Half-Bridge Stage FET stresses are reduced, to
Vout * N. (2x less than the Push-Pull)

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© 2003 National Semiconductor Corporation
 Cascaded Full-Bridge Concept
Vout
Full-Bridge
Stage

Buck T1
Stage
Vin L1
33 - 76V
VDD VDD
VDD
Vcc
Vin HD T1

LD
LM5102 LM5100 LM5100
LM5041

PUSH

PULL
COMP
FEED
BACK
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© 2003 National Semiconductor Corporation
 Cascaded Full-Bridge
Characteristics
• A Cascaded Full-Bridge Converter is a Buck type
converter consisting of a Buck Regulation stage
followed by (cascaded by) a Full-Bridge Isolation
Stage
• The isolation stage is Current-Fed
• No voltage splitter capacitors or output stage
inductor are required as in the Cascaded Half-Bridge
• Overlap time is required for Isolation Stage switches
• The Full-Bridge Stage voltage stresses are Vout x N,
similar to the half-bridge
• Full-Bridge Stage current levels are half that of a
Half-Bridge.

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© 2003 National Semiconductor Corporation
 High Side Gate Driver Operation
VIN VIN

Vcc Vcc
Q2 Q2
LEVEL LEVEL
HI SHIFT HI SHIFT

Vcc Vcc

Q1 Q1

LI LI

• Initially Q1 is activated by Low Side control • Floating Vcc, referenced to Q2 source, is

• Cboot is charged from Vcc through D1, Q1
• Cboot is charged to (Vcc-Vdiode)
available for upper gate driver
• Q2 Gate drive voltage is provided by Cboot
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© 2003 National Semiconductor Corporation
 LM5100, LM5101 High Voltage
Buck Stage Gate Driver
Features Typical Applications
• 2-Amp Driver for High and Low Side N- • Cascaded Power Converters
Channel MOSFETs • Half Bridge Power Converters
• Full Bridge Power Converters
• Independent inputs (TTL-LM5101, CMOS-
• Two Switch Forward Power Converters
LM5100)
• Active Clamp Forward Power Converters
• Bootstraps supply voltage to 116VDC
HB
• Short Propagation Delay (45ns)
• Fast Rise, Fall times (10ns into 1nF) HO
LEVEL
• Unaffected by supply glitching, HS ringing UVLO
SHIFT
• VDD Supply under-voltage lock-out (6.7V) HS
HI
• Low power consumption (1.5mA @ 0.5MHz)
Vcc
• Pin for pin compatible with HIP2100 / 2101
UVLO
LO
Package: SOIC-8, LLP-10 (4x4mm) LI
Vss
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© 2003 National Semiconductor Corporation
 LM5102 Driver with Adjustable
Leading Edge Delay
Features Typical Applications
• 2-Amp Driver for High and Low Side • Cascaded Power Converters
MOSFETs • Half and Full Bridge Power Converters
• Independently Adjustable Leading Edge • Two Switch Forward Power Converters
Delays • Active Clamp Forward Power Converters
• Bootstraps drive high side gate to
116VDC VDD

• Short Propagation Delay (45ns) HB

• Fast Rise and Fall times (10ns into 1nF) HO
• VDD Supply under-voltage lock-out HI DLY HS
Logic
(6.7V)
LI LO
• Low power consumption (1.5mA @ DLY
Logic
0.5MHz)
Packages: MSOP-10, LLP-10 (4 x 4mm)
RT1 RT2

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© 2003 National Semiconductor Corporation
 LM5102 Timing Diagram

HI
K x RT1
HO
LM5102
LI
Adjustable Leading
Edge Delay K x RT2
LO

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© 2003 National Semiconductor Corporation
 LM5104 Driver with Adaptive
Deadtime, Programmable Delay
Features Typical Applications
• 2Amp Driver for Complementary High and • Cascaded Power Converters
Low Side FETs • High Voltage Buck Regulators
• Adaptive Deadtime with programmable • Active Clamp Forward Power Converters
additional delay VDD
• Single TTL-Level logic input LM5104 HB
• Bootstraps drive high side gate to 116VDC Adapt DLY HO
• Short propagation delay (45ns) Logic Logic
HS
• Fast rise and fall times (10ns into 1nF)
• VDD supply under-voltage lock-out (6.7V)
• Low power consumption (1.5mA @ IN Adapt DLY LO
0.5MHz) Logic Logic

Packages: SOIC-8, LLP-10 RT

IN
K x RT TPROP
HO
TPROP K x RT
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LO © 2003 National Semiconductor Corporation
Summary:
New 100V controllers and drivers enable
higher performance power converters with a
minimum of external components:
LM5030 Push Pull Controller
LM5041 Cascade Controller
LM510X Gate Drivers
Questions or Comments?
http://www.national.com/appinfo/power/hv.html
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