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Analog-Digital Converters
Online Seminar
Fall 2002
The World Leader in High-Performance Signal Processing Solutions
A/D Fundamentals
Sampling
Quantization
Factors Affecting A/D Converter Performance
Static Performance
Dynamic Performance
ADC Architectures
SAR ADCs
Pipelined ADCs
Flash Type ADC
Sigma-Delta ADCs
High Speed ADC Application Considerations
The Measurement & Control Loop
n
bits
ANALOG A-D
MUX SIGNAL CONVERTER
PROCESSOR
Digital
Value
time time
Analog Input
DIGITAL OUTPUT CODE = x (2N - 1)
Reference Input
y(t)
y(n)
y(n+1)
AMPLITUDE
QUANTIZATION
t
n-1 n n+1 n+3 ts
DISCRETE
TIME SAMPLING
Quantization Process
Quantization Process
Representing an analog signal having infinite resolution with a digital
word having finite resolution
Determines Maximum Achievable Dynamic Range
Results in Quantization Error/Noise
100 1LSB
11
Digital
10
01 Any Analog Input in this
Range Gives the Same
00 Digital Output Code
111
DIGITAL OUTPUT
110
101
100
011 1 LSB
010
001
111
DIGITAL OUTPUT
110
101
100
011
010
001
q = 1 LSB
0 volts
-q/2
The RMS value of the quantization noise sawtooth is its peak value,
q2, divided by 3, or q 12
For Sine Wave Full Scale RMS Value is 2(N-1)/2
For Saw Tooth Quantization Error Signal RMS Value is q /12
Thus S/N is 1.225 x 2N
Expressed in dB as 1.76 + 6.02N, where N is the resolution of the
A/D converter
Quantization Noise (con’t)
HARMONICS OF FSIGNAL
(EXAGGERATED FOR CLARITY)
OUTPUT
RMS
QUANTIZATION NOISE
FSIGNAL FS/2 FS
0 0 0
ALL ALL
"1"s "1"s
1 AND ALL "0"S
ACTUAL
ACTUAL GAIN
ERROR
IDEAL IDEAL
ZERO ERROR
ACTUAL ACTUAL
IDEAL IDEAL
0 0
Digital Output
101
For this 3-bit ADC, 1 LSB =
(1V/23 = 1/8th) 100
001
000
0 1/8 1/4 3/8 1/2 5/8 3/4 7/8
Analog Input
DC Specifications (DNL)
DifferentialNon-Linearity
ADC Transfer Function
(DNL) is the deviation of an (DNL Error)
Digital Output
101
+1/2 LSB
010
noise/spurs beyond the
effects of quantization 001
000
0 1/8 1/4 3/8 1/2 5/8 3/4 7/8
Analog Input
DC Specifications (DNL)
Digital Output
101
000
0 1/8 1/4 3/8 1/2 5/8 3/4 7/8
Analog Input
DC Specifications (INL)
POWER
LOW PHASE
SUPPLIES
JITTER
SAMPLING
CLOCK SOURCE
A/D CONVERTER
BANDPASS FFT
LOW PHASE ON
FILTER ANALYZER
JITTER EVALUATION BOARD
SINEWAVE SOURCE
amplitude
3f1
f1 2f1 3f1
frequency
An M-Point FFT
0 dB
The Effective Noise Floor of an M-Point FFT Is Less Than The RMS Value
of the Quantization Noise
Actual FFT Plot for AD7484, 14-Bit SAR
ADC Sampling at 3MHz
0
fIN = 1.013MHz
-20
SNR = 77.7dB
SNR+D = 77.6dB
THD = -95.5dB
-40
-60
dB
-80
-100
-120
-140
0 200 400 600 800 1000 1200 1400
Frequency (kHz)
Nyquist Bandwidth & Aliasing
signal
passband
The Signal Frequency Is < 1/2 the Sampling Frequency and So the Sum
and Difference Components Fall Outside (Beyond) the Signal Passband
The Nyquist Bandwidth & Aliasing
(FSIGNAL > ½ FSAMPLING)
The Signal Frequency Is > 1/2 (approx 2/3) the Sampling Frequency. An
“Alias” or False Image is Thus Created that Falls Within the Passband of
Interest.
SINAD, ENOB, and SNR
ANALOG EOC OR
COMPARATOR
INPUT DRDY
SHA +
-
SAR*
START
CONVERT
DAC
*SUCCESSIVE
APPROXIMATION
REGISTER
DIGITAL
OUTPUT
Successive Approximation ADC
+FS
Analog
Input
Analog
Input
-FS
Bit 4 0 0 0 test at 1 0 0 0
VIN > 5.000V VIN > 7.500V VIN > 6.250V VIN > 6.875V
YES NO YES NO
1 0 1 0
Successive Approximation ADC
•Industrial control
•Data acquisition
Pipelined Sub-ranging ADC
FLASH ADC
6
DAC ADC
BUFFER
2nd Stage ADC is 7-bit
7
REGISTER
6
Flash ERROR CORRECTION LOGIC
correction) 12
Pipelined Sub-ranging ADC
+FS
Analog
Input
-FS
•Medical imaging
•Radar
Flash or Parallel ADC
ANALOG
1-BIT,
1-BIT DATA Kfs
1-BIT STREAM
DAC
–VREF
SIGMA-DELTA MODULATOR
OVERSAMPLING, DIGITAL FILTERING,
NOISE SHAPING, AND DECIMATION
A fs Nyquist QUANTIZATION
Operation NOISE = q / 12
ADC q = 1 LSB
Oversampling fs fs
+ Digital Filter 2
B Kfs
+ Decimation
fs
DIGITAL FILTER
DIGITAL
ADC DEC REMOVED NOISE
FILTER
fs Kfs Kfs
Oversampling
+ Noise Shaping 2 2
+ Digital Filter
C + Decimation
Kfs fs
REMOVED NOISE
SD DIGITAL
DEC
MOD FILTER
fs Kfs
Kfs
2 2
DEFINITION OF "NOISE-FREE"
CODE RESOLUTION
16.5bits 0.4uVrms
DNL Effects
EFFECTS OF APERTURE AND SAMPLING
CLOCK JITTER
Jitter:
Most systems assume the signal is sampled uniformly
Clock noise leads to non-uniform sampling (i.e. jitter)
100 tj = 1 16
1ps SNR = 20log10 2ftj
14
80 tj =
10p
s 12
ENOB
SNR
(dB) 10
60 tj =
100
ps
8
tj =
40 1ns 6
4
20
0
1 3 10 30 100
FULLSCALESINEWAVE INPUT FREQUENCY (MHz)
EFFECTIVE APERTURE DELAY TIME
-FS
+te -t e
SAMPLING
CLOCK
te
ADC LATENCY OR PIPELINE DELAY
ANALOG
INPUT
CLK input 90
SFDR-Clock Stabilizer ON
85
CLK oscillators are usually
specified as 40/60 or 45/55 80
Digital Specifications of 75
SINAD-Clock Stabilizer ON
SFDR-Clock Stabilizer OFF
datasheet provide a 70
dBc
minimum CLK HIGH/LOW 65
rated performance. 55
SNR/THD graphs as a
function of duty cycle 45
30 35 40 45 50 55 60 65 70
SFDR
ENABLED
DISABLED
Example : AD9433 SFDR
SFDR
ENABLED
DISABLED
Encode = 105Msps
Ain = 70MHz, -0.5dBFs
Example of Data Sheet Specifications for
AD9430 ADC
Example of Data Sheet Specifications for
AD7476 ADC
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