Performance of Wavelet Based Medical Image

Fusion on FPGA Using High Level Language

‘C’

By
Dr. K. UMAPATHY,
Associate Professor,
Department of Electronics & Communication Engineering,
SCSVMV University,
Kanchipuram, Tamilnadu,
India.
 Abstract
 Implementation of wavelet based medical image fusion on FPGA
performed using ‘C’.
 The Instruction set of the image processor based on the operation of
image algebra like convolution, additive max-min, multiplicative
max-min etc to increase the speed.
 The FPGA based microprocessor & C Programming used for
extraction of texture features and hardware design respectively.
 The programming interface of the user and the approach for
generating FPGA architectures for the image co-processor.
 Sample implementation results (speed, area) for different
neighborhood operations.
 Introduction
 Image fusion - combining relevant information from two or more images into
a single image.
 Resultant image more information than input images.
 Used for medical applications to get a better image.
 Used in automotive industries to enhance the vision of road during a rainy
weather.
 Interpret the image data & obtain a more suitable image for a variety of
applications - Visual interpretation, Satellite, Digital classification & War-field.
 Medical imaging – to obtain a high resolution image for the sake of
diagnosis.
 Fusion of MRI & CT images of the same organ result in an integrated image of
much more information.
 Wavelet transform fusion - applying fusion with the wavelet transforms of the
two registered input images together.
 Pixel Level Image Fusion
 Image fusion process carried out at various levels.
 Pixel-level image fusion – provides all relevant information present in original
images without any inconsistencies.
 Classified into Spatial domain fusion & Transform domain fusion.
 Spatial Domain Fusion - directly applied on the source images - reduces the
signal to-noise ratio of the resultant image with simple averaging technique -
but persists in the fused image.
 Transform Domain Fusion - the input images decomposed into some levels
based on transform coefficients.
 Fusion technique applied and then fusion decision map obtained.
 Using Inverse transformation on this decision map gives the fused image.
 The fused image includes all the details of the source images & reduces the
spatial distortion.
 Field Programmable Gate Array (FPGA)
 Field Programmable Gate Arrays - reconfigurable devices.
 Hardware design techniques such as parallelism & pipelining techniques
developed on a FPGA.
 Implementing image processing algorithms on FPGA - minimizes the time-to-
market cost, enables rapid prototyping of complex algorithms and simplifies
debugging & verification.
 ideal choice for implementation of real time image processing algorithms.
 configured by hardware engineers using a Hardware Design Language (HDL).
 Two principal languages – Verifying Logic (Verilog) & Very High Speed
Integrated Circuits HDL (VHDL) - to design at various levels of abstraction.
 Related Work
 Multiple efforts made to develop new image fusion techniques.
 Image fusion system based on Wavelet Decomposition used for
Unmanned Airborne Vehicles (UAVs).
 FPGA implementation using pyramid landed composition & subsequent
fusion of dual video streams.
 This can fuse dual video streams in gray scale video graphics array
(VGA), with 30 frames/s in real time.
 Both hardware designs showed an improvement in speed performance
compared to respective algorithms.
 Image Algorithm
 Median Filtering - a non-linear digital filter to preserve sharp signal changes &
effective in removing impulse noise
 Linear filters – not to remove this type of noise without affecting distinguishing
characteristics of the signal.
 Median Filters - widely used in Digital signal & Image/video processing
applications.
 Techniques commonly used in all Image processing algorithms are:-
(a) Median Filtering.
(b) Morphological operations.
Median and Median Filter
 Proposed Algorithm
 Consists of median or spatial filter, fuzzy based edge detector ,fusion block.
 Input pixels of input images filtered by Mean filter to enlarge the edges & remove the
noise.
 Edge detected images fused into a single image & then clipping circuit used.
 Followed by feature extraction circuit & minimum distance classifier circuit.
 Finally the fused image classified as normal or abnormal image.
 Step I: Sort elements of each column in the ascending order.
 Step II: Sort elements of each row in the ascending order.
 Step III: Sort the cross diagonal elements & pick up the middle element as the median
element of the window.
 Minimum is the first & Maximum is the last element in the window of the nine elements.
Proposed Algorithm

Block diagram of Design implemented on FPGA

 Implementation
 Entire implementation of Image acquisition, Image processing & Image
retrieval already shown.
 To reduce complexity of Data transactions, RAM implemented on FPGA.
 UART implemented to felicitate Data Acquisition & Communication
between PC and FPGA board.

Simulation Results of RAM

 Results & Discussions
 Dataset includes - color PET scan images & normal brain MRI images.
 Both scan images have a resolution of 256×256 with 8-bit precision in
the luminance channel. T
 Metabolisms exposed by the PET scan fused with the anatomical
structures in MRI scan in the final image - provides an enhanced
spatial relationship.
 The original image & the fused image compared by PSNR (Peak
Signal to noise ratio), MMSE (Minimum mean square error), entropy
& elapsed time.
 Proposed fusion algorithm & hardware architecture system
designed and tested on Spartan-3E using Modelsim 6.1 & Xilinx 9.2i.
 Results & Discussions (Contd)

 Proposed scheme utilized ’17’ LUTs & ‘9’ slices at a maximum

frequency of 100 MHz.
 System incorporated with hardware architecture leads to
lower power consumption in slices, Look Up Tables & Flip Flops
results.
 Proposed fusion architecture implemented in 90 nm CMOS
technology.
Simulation Results for Proposed System RTL
Schematic View Chip Layout
 Results for Proposed Architecture

Technology CMOS 90 nm

Clock frequency 100 Mhz

Power consumption 152 mW

Memory size 174572 kB

 Conclusion
Implementation of wavelet based medical image fusion on FPGA
using high level language C.
Image processor high- level instruction set based on the operation
of image algebra.
FPGA based Microprocessor used to accelerate the extraction of
texture features & High level C programming language used for
hardware design.
Hardware realization based on FPGA provides a fast, compact, &
low-power solution for image fusion.
 References
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THANK YOU