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CMOS VLSI
Design
Lecture 9:
Circuit Families
David Harris
1.5
load
P/2 1.2
P = 24
Ids Vout 0.9
Vout 0.6
16/2 0.3
P = 14
P=4
Vin
0
0 0.3 0.6 0.9 1.2 1.5 1.8
Vin
gu = gu = gu =
gd = g = gd =
gavg = Y gd = gavg =
avg
pu = A pu =
Y Y pu =
A pd = B pd = A B pd =
pavg = pavg = pavg =
gu = gu = gu =
gd = 2/3 g = gd =
gavg = Y gd = gavg =
2/3 avg 2/3
pu = A 8/3 pu =
Y Y pu =
A 4/3 pd = B 8/3 pd = A 4/3 B 4/3 pd =
pavg = pavg = pavg =
en
Y
A B C
2 2/3 1
A Y Y Y
1 A 4/3 A 1
precharge transistor
Y Y
Y inputs inputs
A f f
foot
footed unfooted
1
Y
1 1
A 2
unfooted Y Y
A 1 B 2 A 1 B 1
gd = gd = gd =
pd = pd = pd =
1
Y
1 1
A 3
Y Y
footed A 2 B 3 A 2 B 2
gd = gd = gd =
2 pd = 3 pd = 2 pd =
1
Y
1 1
A 2
unfooted Y Y
A 1 B 2 A 1 B 1
gd = 1/3 gd = 2/3 gd = 1/3
pd = 2/3 pd = 3/3 pd = 3/3
1
Y
1 1
A 3
Y Y
footed A 2 B 3 A 2 B 2
gd = 2/3 gd = 3/3 gd = 2/3
2 pd = 3/3 3 pd = 4/3 2 pd = 5/3
A
– 0 -> 1
– 1 -> 1
violates monotonicity
– But not 1 -> 0 during evaluation
A
A=1
A=1
domino AND
W
W X Y Z X
A
Y
B C
Z
dynamic static
NAND inverter
A W X A X
H Y =
B H Z B Z
C C
S0 S1 S2 S3
D0 D1 D2 D3
Y
H
S4 S5 S6 S7
D4 D5 D6 D7
1 0 ‘1’
1 1 invalid
Y_l Y_h
= A*B A_h = A*B
A_l B_l B_h
Y_l Y_h
= A xnor B A_h A_l A_l A_h = A xor B
B_l B_h
Y A
A x CY
Y
B=0 Cx
Y A
A x CY
Y
B=0 Cx Charge sharing noise
Vx VY
Y A
A x CY
Y
B=0 Cx Charge sharing noise
CY
Vx VY VDD
C x CY
secondary
precharge
Y transistor
A x
B
A A
S Y S Y
B B
S S
S
A
S L Y
B
S
A
S L Y
B
S
A
S L Y
B