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测试原理
Unit 1:
Introduction to Flash
Technology
Overview of Memory Devices
Course
Contents
Two Basic Memory Categories
Nonvolatile Memory非易挥发存储器
• Data remains even when power is removed.
Volatile Memory
Bit line
Word line
Bit line
Word line
Bit line
Bit line
Bit line
not charged,
current flows
on bit line
–Buffer on
column sense
amps
Word line
Bit line
Bit line
Bit line
Floating gate
Floating Gate
Polysilicon
Dielectric (ONO)
Control Gate (doped)
Dielectric (oxide)
Floating Gate
n+ Source n+ Drain
p+ Substrate
Flash Cell Operation - Program Mode
Channel Hot-Electron Injection
VG = +9.3V
Electric fields form
due to voltages
Control Gate
GND VD = +4.5V
Floating
E-fieldGate
E-field
n+ Source Drain n+
p+ Substrate
Flash Cell Operation - Program Mode
Channel Hot-electron Injection
VG = +9.3V
Control Gate
GND VD = +4.5V
Floating
e
e - e -Gate
e-- e-
e
e- e- e- e- - e-
n+ Source e- e- e e- Drain n+
p+ Substrate
Flash Cell Operation - Program Mode
IDS Conduction & Floating Gate Charge (Q)
VG = +9.3V
Logic state “0”
Q Control Gate
GND VD = +4.5V
Floating Gate
n+ Source Drain n+
IDS
=0
p+ Substrate
Flash Cell Operation - Erase Mode
Negative Gate ---F-N Tunneling
Electrically-erasable
VG = -9.3V charge from gate
Logic state “1”
Q Control Gate
Float VD = Float
Floating
e- e- e- e-Gate
e-
n+ Source e- e- e- e- Drain n+
e-
p+ Substrate
Flash Memory Bit Threshold Voltages
IDS
0 1 2 3 4 5 6 7
VGS
Flash Array Architecture (schematic)
S
R o
o u
w r
Address c
D e GND
e
c S
o w
d i
e t
r c
h
Selected cell
Column Decoder
Basic Memory Device
Internal Architecture
Memory cell
A4 A5 A6 A7
A0 1 0 0 0
A1 0 1 0 0
A2 0 0 1 0
A3 0 0 0 1
• DC parametric test
• AC parametric test
• Functional Test
DC parametric test
DC Parametric Tests:测试 Address Decoder 和 I/O 回路 中Input/Output Buffer
的DC特性。
No current No current
through two through
In (0.3V) In (0.3V)
protect diode two protect
diode
I I
Vss (0 V)
Vss (0 V)
Definition
IIL -- Input leakage low
The current in an input when it is forced low voltage.
IIH -- Input leakage high
The current in an input when it is forced high voltage.
Why test?
Measure I
VSS = 0V
• Apply VCCmax.
• Preconditioning all inputs to logic 1 with pin drivers.
• Input disable
• Using PMU, force individual inputs to VSS.
• Measure the current flows from VCC to the pin being tested.
• Repeat the same test on each pin.
• Fails IIL if measured current is outside of the spec.
Input Leakage High Test---IIH
Pin Electronics Force
Test Method Logic 0 on all inputs
VCCmax
PMU 3.5V
DUT
DUT
Input
Force VCCmax V Pin
Measure I IIH
VSS= 0V
• Apply VCCmax.
• Preconditioning all inputs to logic 0 with pin drivers.
• Input disable
• Using PMU, force individual inputs to VCC.
• Measure the current flows from the pin being tested to VSS.
• Repeat the same test on each pin.
• Fails IIH if measured current is outside of the spec.
Output Leakage Test ---IOL
Purpose: To measure the output current leakage (1uA spec)
Test Method
• Apply VCCmax.
• Preconditioning all Outputs to logic 1 with pin VCCmax
drivers.
• Output Disable ON
IOL
• Using PMU, force individual inputs to VCC.
• Measure the current flows from the pin being 0.0
tested to VSS.
v
• Repeat the same test on each pin. OFF
Test Method
• Apply VCCmax.
VCCmax
• Preconditioning all Outputs to logic 0 with
pin drivers. OFF
• Output Disable
3.5v
• Using PMU, force individual inputs to VCC.
• Measure the current flows from the pin
IOH
being tested to VSS. ON
• Repeat the same test on each pin.
• Fails IOH if measured current is outside of VSS=0V
the spec.
CMOSASM Test
Purpose:
This test checks the CMOS Automatic Sleep Mode. It is a guardbanded
tests using a Vcc which is 15-30% higher than Max. Vcc and tests
against a limit of 10% guardband). The input pins are biased at the
worst possible condition as well (lowest VIH and highest VIL).
•VOH/IOH
•VOL/IOL
Output voltages testing---VOH/IOH
Definition
VOH -- represents the minimum voltage (V) produced by an output (O) when
the output is in the logic 1 (High) state.
IOH -- represents the current sourcing capabilities (I) of an output (O)
when the output is in the logic 1 (High) state.
Why test?
DUT
VCCmin
Test Method IOH PMU
ON DUT Force I
Output
Pin Measure V
OFF
VSS=0V
•Apply VCCmin.
•Precondition output to logic 1 (output high).
•Using PMU, force IOH current per specification.
•Wait 1 to 5 msec (Set PMU delay).
•Measure resultant voltage.
•Fails VOH of measured voltage is less than the limit.
Output voltages testing---VOL/IOL
Definition
Why test?
DUT
VCCmin
Test Method PMU
DUT
OFF
Output Force I
ON Pin
Measure V
IOL
VSS=0V
•Apply VCCmin.
•Precondition output to logic 0 (output low).
•Using PMU, force IOL current per specification.
•Wait 1 to 5 msec (Set PMU delay).
•Measure resultant voltage.
•Fails VOL of measured voltage is greater than the limit.
AC Parametric Testing
•Rise and Fall time - To guarantee that output data rise and fall rate.
AC parametric test---Setup Time TSD
•Setup time - TSD to guarantee that input data can be read within a
minimum amount of time before a reference signal occurs.
AC parametric test--- Hold Time THD
•Hold time - THD to guarantee that input data can be read within a
minimum amount of time after a reference signal occurs.
AC parametric test--- Program Delay Time
• Stuck-At Fault
• Transition Fault
• Coupling Fault
• NPSF Neighborhood Pattern Sensitive Fault
Stuck-At Fault
• READ0/READALL+EMBERASE+BLANK
• PRGDIAG
• VERDIAG
• PRGRVCK
• RVCKSP
• PRGSP1 / 2
• PRGCKBD
READ0/READALL+PREERASE+BLANK
Description:
These test blocks work together to insure the array is
blank before testing continues. A portion of the array
is read using READ0 or READALL (depending on the
flow). Devices which fail this initial blank check are
PREERASE, and then the erase is verified with a full
Blank Check.
PRGDIAG *
Description:
•In Figure , the array on the right has a metal short between columns
(bitlines) 2 and 3. The short accidentally shares the programming drain
voltage between the two columns. The programming wordline voltage is
common across a row, so programming any bit in column 2 accidentally
programs the adjacent bit in column 3.
This is called
bit pickup
PRGRVCK --- Programming Reverse CKBD
Description:
01 0 0
10 0 0
0 0
11
RVCKSP *--- Reverse CKBD Speed
Description:
•RVCKSP tests AC speed by reading the RVCK pattern with tight timing.
•There are usually six speed grades. The program tests units starting
with the fastest speed bin, and moving through the six grades until
finding a passing bin.
• The actual speed values of the six bins vary from program to program,
depending on the speed distribution of the part and Marketing
requirements.
An example of 3V speed grades is shown below:
PRGSP1 / 2 * --- Program Speed
Description:
•The PRGSP1/2 blocks test the AC write parameters
•It Embedded Programs one row and one column using tight timing
parameters and address/data formatting.
Programs a CKBD pattern, which alternates 1’s and 0’s through the entire
array. This checks the programmability of half the array. The surrounding
blank bits are NOT read in this test, they are checked in Checkerboard
Verify.
PRGCKBD *--- Programming Checkerboard/
Check board verify
Checkerboard Verify Description:
Reads both 1’s and 0’s of the CKBD pattern. The CKBD pattern is
designed to reveal bit-to-bit shorts, typically caused by poly 1 to poly 1
shorts. Unlike metal shorts which affect entire columns, the poly 1
shorts only affect bits adjacent to the short. So every pair of bits must
be checked. By alternating 1’s and 0’s through the whole array, the
CKBD pattern accomplishes this task.
Class Test Flow
Parametrics Opens, Shorts, Icc power tests, Input / Output Lkg
System Clocks
and Calibration
Circuits
Test Head Pin
Electronics
Drivers,
CPU with Hard
Comparators,
Disk, Tape
Current Loads,
Drive, Keyboard Internal System
DPS and etc.
& Video Controll Power Reference
er CPU Supplies Supplies
(for VCC, VIL,
VIH, VOL, VOH)