Xilinx FPGAs:Evolution and Revolution

 Evolution results in bigger, faster, cheaper

FPGAs; better software with fewer bugs, faster
compile times; coupled with better technical
support.
 Innovative architectural and circuit features with
advancements in design methodology - modular
team based design & internet based configuration
method: resulting in Revolution.
A Decade of Progress
Xilinx FPGAs : An Endless Journey
XC2000
1.5K

7.5K, 50MHz XC3000 XC3100

85K, 80 MHz

XC5200
0.5 micron XC4000 SPARTAN
16K, 50MHz 0.5 micron 0.35, 0.25 m 100MHz+
40K

50K-1M, VIRTEX SPARTAN-II

200MHz 0.22micron 0.22 micron
200K, 200MHz

4M, VIRTEX-E SPARTAN-IIE

0.18micron 0.18micron
250MHz 300K,
200MHz+

VIRTEX-II
40K-8M, 0.15 micron
420MHz

VIRTEX-II
10M, PRO
420MHz 0.13micron
Xilinx FPGAs - Generic Features
 High Performance at different voltages
 Footprint Compatibility
- Devices within each family are compatible.
 Low power consumption/high performance
 Integrated Software
 Technology independence
- EDIF, VHDL, Verilog, SDF interfaces.
XC2000
 First FPGA Family from Xilinx.
 Two members:
XC2064 1000 Gates
XC2018 1500 Gates
 Ext. Crystal Oscillator.
 No Tri State Buffers.
 XACT 1.0 Development System.
XC2000
 Max.Logic Gates 1500
 Max. CLB Flip-flop 100
 Max. I/O Pins 74
 Max. I/O Flip-Flop 74
XC3000
 Replaces TTL, MSI and other PLD logics.
 Integrates complete subsystem into single
Package.
 System clock Speed up to 50 MHz.
 On-chip crystal Oscillator.
 Low-Skew Clock Nets.
 Over 20 different Packaging Options
 Interface to popular design Environment like
Mentor, Cadence and View Logic.
XC3000 CLB
XC3100A
 Ultra-high-speed Family with six members.
 XC3195 in 22 X 22 CLB array size.
 Compatible with XC3000.
 Error checking of configuration bit stream.
XC4000 CLB
XC4000 Family Features
 Synchronous Single and Dual-Port RAM
 Internal Three-state buffers.
 JTAG Boundary Scan
 System performance to 80 MHz
 0.5 µ SRAM Process Technology
XC4000 Sub-Families
Version Max. logic Max. I/O Voltage
Gates

XC4000XL 3k-85k 448 3.3

XC4000EX 28k, 36k 320 5
XC4000E 3.0-25k 256 5
XC5200
 Low Cost FPGA Family.
 System Features:
- Fast Arithmetic Functions
- High Performance Clock Network
- Highly routable
- Easy Pin Locking
- Fast wide Functions
- Three-state buffers
- JTAG
- Performance up to 50 MHz.
Resource Comparison
 Xilinx Spartan/XL FPGAs
Xilinx 4000 Advanced Process
Series
Heritage Technology

100 MHz+ performance Small die size

On-chip SelectRAM
Software v4.2i
Core solutions
Low cost packaging
Low test cost
Total Cost
 Total Cost Management
 Leading edge process technology
 Smallest die size of any FPGA with on-chip RAM
 Focused package offering
 Low-power architecture allows use of highest volume
plastic packages
 Streamlined test flow
 Lower cost test hardware
 Built-in self test features and shorter test times
 Optimized manufacturing flows
 Spartan-XL Family
Advanced 0.35m Process
 Transistor gates 0.35u
 Allows 3.3 V supply
 All other features 0.25u
 Small size
 Low capacitance
 Performance

Chip

Combines 3.3 V operation with 0.25u benefits

 Spartan Speed Grades
 Higher speed grade = higher performance
XL-5

E-1 -4 XL-4
Performance

E-2 -3

-3

-4
XC5200 XC4000E Spartan Spartan-XL
What’s missing in Spartan?
 No asynchronous RAM
 Only RAM16(32)X1S, RAM16X1D, ROM16X1
 No edge decoders
 No DECODEx
 No wired-AND
 No WANDx or WOR2AND
 Mode pins not usable as I/O
 No MD0, MD1, MD2
Virtex - features
 Densities from 50 K to 1M system gates.
 System performance up to 200 MHz.
 Multi-standard Select IO interfaces.
 Built-in clock-management circuitry
- Four DLLs
- Four Low-skew global Clock Distribution Net
 Hierarchical Memory System.
 Dedicated Multiplier Support.
Spartan-II - features
 Densities as high as 200K gates.
 Streamlined features based on Virtex architecture.
 Very Low Cost
 LUT Distributed RAM and Block RAM support.
 Dedicated Multiplier support.
 4 DLLs
 Virtex/Spartan-II CLB
 1 CLB holds 2 slices
 Each slice has two sets of
 Four-input LUT
 Any 4-input logic function
 Or 16-bit x 1 RAM
 Or 16-bit shift register
 Carry & Control
 Fast arithmetic logic
 Multiplier logic
 Multiplexer logic
 Storage element
 Latch or flip-flop
 Set and reset
 True or inverted inputs
 Sync. or Async. Control
 Virtex/Spartan-II DLLs Improve
Clock Networks
Deskew
DLL1 DLL2 Clocks
Deskew
on Board
Clocks Cascade
Manage Multiple on Chip DLLs
System Clocks
Convert
Clock
DLL3 DLL4 Levels
Generate using
Clocks Select I/O
(Multiply,
Divide, or
Shift)

Delay locked loops synchronize on-chip and board level clocks

Virtex-E – what’s added?
 Up to 4 million system gates
 2-4X more Block RAM
 8 DLLs
 Differential I/O signaling (LVDS/BLVDS)
 some new speed grades.
Spartan-IIE - features
 Density 50-300K
 Supports LVDS
 4 DLLs
 VCCINT – 1.8V
 More speed grades than Spartan-II.
 Less packaging Options.
Virtex-II
 All Xilinx FPGAs contain the same basic resources
 CLBs contain combinatorial logic and register resources
 IOBs interface between the FPGA and the outside world
 Programmable interconnect
 Other resources
 Three-state buffers
 Global clock buffers
 Boundary scan logic
 Virtex-II devices contain additional resources
 Block SelectRAM
 Dedicated Multipliers
 Digital Clock Manager (DCM)
CLB Tile COUT COUT
TBUF
TBUF

Slice S3

Slice S2
Switch SHIFT
Matrix

Slice S1

Slice S0 Fast Connects

CIN CIN
Slice Structure
Slice 0

PRE
LUT Carry D Q
CE

CLR

LUT Carry PRE

D Q
CE

CLR
 Mult-AND and dedicated Multiplier too
 SRL16
 DDR Registers.
 Fast Carry Logic
 Digitally Controlled Impedance
Connecting Function Generator
CLB

F8
F5
Slice S3

F6
F5
Slice S2
F7

Slice S1
F5
F6

Slice S0
F5
 Select I/O
 Allows direct connections to external signals of varied
voltages and thresholds
 Optimizes the speed/noise tradeoff
 Saves having to place interface components onto your
board
 Differential signaling standards
 LVDS, BLVDS, ULVDS
 LDT
Distributed and Block Select RAM
RAM16X1S
D
WE
WCLK
LUT A0 O
A1
A2
A3

RAM32X1S RAM16X1D
D D
WE WE
WCLK WCLK
Slice A0 O A0 SPO
A1 A1
A2 A2
LUT A3 A3
A4 DPRA0 DPO
DPRA1
DPRA2
DPRA3

LUT
Dedicated Multiplier Block
 Eighteen-bit 2’s complement signed operation
 Optimized to implement Multiply / Accumulate functions
 Multipliers are physically located next to block SelectRAM

4x4 signed ~255 MHz

18 8x8 signed ~210 MHz

18xx1818 Output
Multiplier
Multiplier
(36 bits)
12x12 signed ~170 MHz
18x18 signed ~140 MHz
DCM
 Up to twelve DCMs per device
 Located on top and bottom edges of the die
 Driven by clock input pads
 DCMs provide:
 Delay-Locked Loop (DLL)
 Digital Frequency Synthesizer (DFS)
 Digital Phase Shifter (DPS)
 Digital Spread Spectrum (DSS)
 Up to four outputs of each DCM can drive onto global
clock buffers
 All DCM outputs can drive general routing
Challenges to accelerate Processing
performance
Very Large
Single Task Types Multiple Tasks
requires of
Parallel Challenges
Processing

Multiple Solutions

Parallel Processing Using Parallel Processing in Multiple Processors

Multiple Processors Hardware on Multiple Tasks
• High performance • Specific task focus
• lower cost • Scalable
• low complexity
 Virtex-II Pro Addresses All
Processing Tasks
Fabric for parallel
Fabric for parallel
processing in hardware
processing in hardware

Virtex-II
Virtex-II
Pro Fabric
Pro Fabric
•Uunmatched Performance
•Uunmatched Flexibility

Up to four 300MHz PowerPCs

Up to four 300MHz PowerPCs
for multiple processing
for multiple processing
Logic Capacity and Features
Virtex II Pro Leads all the way
Supply Voltage
 XC4000 and Spartan families use a 5V supply.
 The-XL families use 3.3 V supply.
 Virtex and Spartan-II use 2.5V supply.
 Virtex-E uses 1.8 V.
 Virtex-II and Virtex-IIPro uses 1.5 V
Xilinx Development System
XACT 1.0; 2.0
... 6.0

Xilinx-NeoCAD
Merge

M 1.0

M2.0i....M5.1i
THE FUTURE…….
 In 2005, FPGAs will be built on 70nm-Cu
process; will implement 50 million system
gates; with 2 billion transistors on-chip; with
10 layers of copper metal; with embedded
processors running at 1 GHz clock rate; with
direct interface to 10 Gbps serial data.
URLs
 www.xilinx.com
 www.fpga-faq.com
 www.optimagic.com
 www.datasheetlocator.com
 Newsgroup comp.arch.fpga