CHAPTER 6

FIELD EFFECT TRANSISTOR (FET)

Basic construction of an n-channel MOSFET Cross section view of an n-channel MOSFET

 BJT vs. FET
Feature BJT FET

Size Relatively Large Very Small Comparing to BJT

(nm)
Power High Low
consumption
Currents Three Currents (IC, IB and IE) Only one current (ID)

Usage Not much used in modern Widely used in current

technology technology

Symbols of the n-channel Symbols of the p-channel

MOSFET MOSFET
 Symbols of the n-channel MOSFET Symbols of the p-channel MOSFET

Ideal n-channel MOSFET I-V Characteristics (NMOS device)

In saturation region 𝑣𝐺𝑆 > 𝑉𝑇𝑁

𝑣𝐺𝑆 − 𝑣𝐷𝑆 (sat) = 𝑉𝑇𝑁

Or, 𝑣𝐷𝑆 (sat) = 𝑣𝐺𝑆 − 𝑉𝑇𝑁

𝑖𝐷 = 𝐾𝑛 𝑣𝐺𝑆 − 𝑉𝑇𝑁 2

In nonsaturation region 𝑣𝐺𝑆 < 𝑉𝑇𝑁

𝑖𝐷 = 𝐾𝑛 2 𝑣𝐺𝑆 − 𝑉𝑇𝑁 𝑣𝐷𝑆 − 𝑣𝐷𝑆 2

Where 𝐾𝑛 is called the conduction parameter for the n-channel
and represented as follows

𝑊𝜇𝑛 𝐶𝑜𝑥
𝐾𝑛 =
2𝐿
𝐾𝑛′ 𝑊
Or, 𝐾𝑛 = ∙
2 𝐿

Here , 𝐾𝑛′ = 𝜇𝑛 𝐶𝑜𝑥 is called process conduction parameter

𝐶𝑜𝑥 is the oxide capacitance per unit area and related as 𝐶𝑜𝑥 = 𝜖𝑜𝑥 Τ𝑡𝑜𝑥

The Ideal p-channel MOSFET 𝑰 − 𝑽 Characteristics (PMOS device)

𝑣𝑆𝐷 sat = 𝑣𝑆𝐺 + 𝑉𝑇𝑃
2
In saturation region 𝑣𝑆𝐺 < 𝑉𝑇𝑃 and drain current, 𝑖𝐷 = 𝐾𝑝 𝑣𝑆𝐺 + 𝑉𝑇𝑃

In nonsaturation region 𝑣𝑆𝐺 > 𝑉𝑇𝑃 and 𝑖𝐷 = 𝐾𝑝 2 𝑣𝑆𝐺 + 𝑉𝑇𝑃 𝑣𝑆𝐷 − 𝑣𝑆𝐷 2

Where 𝐾𝑝 is called the conduction parameter for the p-channel and it is represented
same as NMOS device only the subscript used as p instate of n
EXAMPLE 6.1

Calculate the current in an NMOSFET. Consider an n-channel enhancement-mode

MOSFET with the following parameters: 𝑉𝑇𝑁 = 0.4V, W = 50μm, L= 2μm, μn= 650
cm2/V-s, tox= 250Å, and 𝜖𝑜𝑥 = (3.9) (8.85 × 10-14) F/cm. Determine the current when
the MOSFET is biased in the saturation region for 𝑣𝐺𝑆 = 2.2V.

Solution: The oxide capacitance

𝐶𝑜𝑥 = 𝜖𝑜𝑥 Τ𝑡𝑜𝑥 = (3.9) (8.85 × 10−14 )Τ 250 × 10−8 = 0.138 × 10-6 F/cm

The conduction parameter of the transistor

𝑊𝜇𝑛 𝐶𝑜𝑥 50×650 ×0.138×10−6

𝐾𝑛 = = = 1.12mA/V2
2𝐿 2×2

So the drain current

2 2
𝑖𝐷 = 𝐾𝑛 𝑣𝐺𝑆 − 𝑉𝑇𝑁 = 1.12 2.2 − 0.4 = 3.63mA
 Non-ideal Characteristic of MOSFET

The slope of the curve in the saturation region can be described by expressing the iD
versus VDS characteristic, for an n-channel device

𝑖𝐷 = 𝐾𝑛 𝑣𝐺𝑆 − 𝑉𝑇𝑁 2 1 + 𝜆 𝑣𝐷𝑆

Where, 𝝀 a positive quantity is called the channel-length modulation parameter

In this figure, at point 𝑣𝐷𝑆 = − 𝑉𝐴 ,

the drain current iD = 0
so, from the equation
1
𝑉𝐴 =
𝜆

The output resistance due to channel length modulation is defined as

𝜕𝑖𝐷 −1
𝑟0 = ฬ where 𝝏 partial differential
𝜕𝑣𝐷𝑆 𝑣𝐺𝑆 =Con.
So, the output resistance evaluated at the Q-point is

1 𝜕 𝐾𝑛 𝑣𝐺𝑆 − 𝑉𝑇𝑁 2 1 + 𝜆 𝑣𝐷𝑆

=
𝑟0 𝜕𝑣𝐷𝑆

2 −1
Or, 𝑟0 = 𝜆𝐾𝑛 𝑉𝐺𝑆𝑄 − 𝑉𝑇𝑁

−1 1 𝑉𝐴
Or, 𝑟0 ≅ 𝜆 𝐼𝐷𝑄 = =
𝜆 𝐼𝐷𝑄 𝐼𝐷𝑄

DC Analyses of the MOSFET Circuit (for NMOSFET)

𝑅2
𝑉𝐺 = 𝑉𝐺𝑆 = 𝑉
𝑅1 + 𝑅2 𝐷𝐷

If VGS > 𝑉𝑇𝑁 then the FET is biased in saturation region

And the drain current, 𝑖𝐷 = 𝐾𝑛 𝑣𝐺𝑆 − 𝑉𝑇𝑁 2

The drain-to-source voltage of the circuit is

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷

Since there is no gate current, the total power dissipation in the MOSFET
is

𝑃𝑇 = 𝑉𝐷𝑆 𝐼𝐷

EXAMPLE 6.2

Calculate the quiescent drain current, drain-to-source

voltage and power dissipation of a common-source
MOSFET circuit as shown in figure.
Assume that 𝑉𝑇𝑁 = 1.3 V and Kn = 0.3 mA/V2
Solution:
𝑅2 20
𝑉𝐺 = 𝑉𝐺𝑆 = 𝑉𝐷𝐷 = ×5=2V
𝑅1 + 𝑅2 20 + 30

Initially assume that the MOSFET is biased in the saturation region, so the drain current

𝑖𝐷 = 𝐾𝑛 𝑣𝐺𝑆 − 𝑉𝑇𝑁 2 = 0.3 × 2 − 1.3 2 = 0.147 mA

The drain-to-source voltage of the circuit is

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 = 5 − 0.147 × 20 = 2.06 V

Since, 𝑉𝐷𝑆 = 2.06 V is greater than 𝑉𝐷𝑆 sat = 𝑉𝐺𝑆 − 𝑉𝑇𝑁 = 2 − 1.3 = 0.7 V,
the NMOS bias is confirmed in the saturation region, as we initially assume.

Power dissipation in the MOSFET is

𝑃𝑇 = 𝑉𝐷𝑆 𝐼𝐷 = 2.06 × 0.147 = 0.303mW

EXAMPLE 6.3

Design an n-channel MOSFET circuit as shown in figure with fulfill a set of conditions
as 𝐼𝐷𝑄 = 0.6 mA and 𝑉𝐷𝑆𝑄 = 3.5 V.

Assume the transistor parameters are 𝐾𝑛′ = 120 μA/V2, 𝑊Τ

𝐿 = 8 and 𝑉𝑇𝑁 = 1.5 V
Solution: Initially assume that the transistor is biased in the
saturation region, so the drain current
2
𝐼𝐷𝑄 = 𝐾𝑛 𝑉𝐺𝑆 − 𝑉𝑇𝑁

𝐾𝑛′ 𝑊 120 × 10−3

Here, 𝐾𝑛 = ∙ = × 8 = 0.48 mA/V2
2 𝐿 2

Therefore, 𝐼𝐷𝑄 = 0.6 = 0.48 × 𝑉𝐺𝑆 − 1.5 2

Or, 𝑉𝐺𝑆 = 0.6Τ0.48 + 1.5 = 2.618 V

So, 𝑉𝐷𝑆 sat = 𝑉𝐺𝑆 − 𝑉𝑇𝑁 = 2.618 − 1.5 = 1.118 V and 𝑉𝐷𝑆𝑄 = 3.5 > 𝑉𝐷𝑆 sat

The NMOS is biased in the saturation region, as we initially assume.

Since the gate current is zero, the gate is at ground potential. The voltage at the
source terminal is the 𝑉𝑆 = −𝑉𝐺𝑆 = − 2.618 V. Then the value of source resistance

𝑉𝑆 −𝑉 − −2.618−(−5)
𝑅𝑆 = = = 3.97 kΩ
𝐼𝐷𝑄 0.6
The voltage at the drain terminal is

𝑉𝐷 = 𝑉𝑆 + 𝑉𝐷𝑆𝑄 = −2.618 + 3.5 = 0.882 V

So the value of the drain resistance is

𝑉 + −𝑉𝐷 5−0.882
𝑅𝐷 = = = 6.86 kΩ
𝐼𝐷𝑄 0.6
 Basic Applications of MOSFET

MOSFET Inverter

If 𝑣𝐼 < 𝑉𝑇𝑁 , the transistor is cutoff and the drain current 𝑖𝐷 = 0, so the 𝑣0 = 𝑉𝐷𝐷 .

If 𝑣𝐼 > 𝑉𝑇𝑁 , the transistor is on and the drain current 𝑖𝐷 ≠ 0.

When 𝑣𝐼 = 𝑉𝐷𝐷 the transistor is biased in the nonsaturation region. In this case the drain
current output are

𝑖𝐷 = 𝐾𝑛 2 𝑣𝐼 − 𝑉𝑇𝑁 𝑣0 − 𝑣02

and 𝑣0 = 𝑉𝐷𝐷 − 𝑖𝐷 𝑅𝐷

NMOSFET inverter circuit

Digital Logic Gates

NOR gate NAND gate

NOR gate response The NAND gate response

𝑉1 (𝑉) 𝑉2 (𝑉) 𝑉𝑂 (𝑉) 𝑉1 (𝑉) 𝑉2 (𝑉) 𝑉𝑂 (𝑉)

0 0 High 0 0 High
5 0 Low 5 0 High
0 5 Low 0 5 High
5 5 Low 5 5 Low
MOSFET Small Signal Amplifier

NMOS common-source amplifier Signal amplification is shown in graphically

Figure shows a simple n-channel enhancement-mode MOSFET amplifier circuit. Voltage

divider bias is used to bias the device in saturation region. The Q-point is selected
approximately in the middle on the dc load line. A small time varying signal 𝑣𝐼 = 𝑉𝐼 sin 𝜔𝑡, is
applied in the input, the gate-to-source is changing over the time, as a result the Q-point will
move up and down on the dc load line. This variation in the output voltage can be larger
than the input signal, which means the input signal is amplified