Architecture of our Microprocessor

Sha.Sa-1
DESIGN DIAGRAM of Sha.Sa-1
IO
INTRPT CONTRL
CONTRL

INSTRTN REGISTER
ACCU FLAG
REGISTER ARRAY

INSTRTN
ALU
DECODER

ADDRESS DATA/ADDRESS
BUFFER BUFFER

TIMING AND CONTROL

MAIN UNITS
• The microprocessor consists of:

– Timing & Control unit : control microprocessor

operations.
– ALU : performs data processing function.
– Registers : provide storage internal to CPU.
– Interrupts : to handle another service temporarily
– Internal data bus : main data path
– Accumulator : to store intermediate results
– Flag : indicates the result of previous operation
– IO controller : controls input/output
 BUS STRUCTURE

MEMORY INPUT
OUTPUT
uP

Data Bus
Address Bus
Control Bus
 CPU Architecture
• CISC (Complex Instruction Set Computer)
- traditional architecture of a computer
- uses microcode to execute very comprehensive instruction set
- variable in length and use all addressing modes (complex decoding circuit)

• RISC (Reduced Instruction Set Computer)

- constant size
- ban indirect addressing
- very fast execution due to simple instruction
- fewer transistors ; cheaper to design
 Instruction Set
• Instruction
- binary pattern designed inside a microprocessor to perform a
specific function.

• Instruction set
- group of instructions

• Instructions can be divided into 5 functional categories

i. arithmetic
ii. logical
iii. Data transfer
iv. Conditional branch
v. Unconditional branch
 Instruction Set
i. Arithmetic
- addition, subtraction, increment or decrement

ii. Logical
- AND, OR, Exclusive – OR, Rotate, Shift, Compare, and Complement

iii. Data transfer

- Load, store word

iv. Conditional Branch

- branch on equal, branch on not equal

v. Unconditional Branch
- jump, jump register
 Instruction Format
• Each instruction has two parts:
i. opcode - task to be performed
ii. operand - data to be operated on

• Instruction execution cycle

Instruction Fetch Instruction Decode Operand Fetch

Next instruction Store Execute

 Instruction Format
• Eg:
opcode
a=b+c

source operands
dest. operands
 Addressing modes

• Addressing modes define the ways

- to get the data for the operands
- put the data into the destination
 Addressing modes
Addressing Syntax Meaning
Mode
Immediate #K K
Direct K M[K]
Indirect (K) M[ M[K] ]
Register (Rn) M[Rn]
Register Indexed (Rm + Rn) M[Rm + Rn]
Register Based (Rm + X) M[Rm + X]
 Endianness
• Multi-byte words are stored in memory location
as a sequence of bytes
• 2- ways
i. big - endian
- MSB at lower byte

ii. little- endian

- LSB at lower byte
 Endianness
• big – endian aAA
BB
AA BB CC DD EE CC
DD
MSB LSB EE a+4

• Little – endian a
EE
DD
AA BB CC DD EE
CC
MSB LSB BB
AA a+4