Combinational Logic Circuit (CLC) Lecture: 07

Course Conducted by Shuvodip Das, Lecturer, Department of ETE, Prime University, Bangladesh.

Combinational Logic Circuit (CLC)

y Computer components are made from both combinational and sequential

logic circuits y We will apply the knowledge of Boolean Algebra to realize these circuits y First we will look at Combinational Logic Circuit y Unlike Sequential Logic Circuits whose outputs are dependant on both their present inputs and their previous output state giving them some form of Memory, the outputs of Combinational Logic Circuits are only determined by the logical function of their current input state, logic "0" or logic "1", at any given instant in time as they have no feedback, and any changes to the signals being applied to their inputs will immediately have an effect at the output. In other words, in a Combinational Logic Circuit, the output is dependant at all times on the combination of its inputs and if one of its inputs condition changes state so does the output as combinational circuits have "no memory", "timing" or "feedback loops".

Combinational Logic Circuit (CLC)

y Always gives the same output for a given set of

inputs y Do not store any information (memoryless)

y A set of m Boolean inputs, y A set of n Boolean outputs, and y n switching functions, each mapping the 2m input

combinations to an output such that the current output depends only on the current input values. y combinational circuits have "no memory", "timing" or "feedback loops".

Combinational Logic Circuit (CLC)

y Combinational Logic

y Combination Logic Circuits are made up from basic logic NAND,

NOR or NOT gates that are "combined" or connected together to produce more complicated switching circuits. These logic gates are the building blocks of combinational logic circuits.

Combinational Logic Circuit (CLC)

Applications or Examples of CLC:

y Multiplexer and Demultiplexer y Adder and Subtractor y BCD Arithmetic Circuit y Arithmetic Logic Unit (ALU) y Digital Comparator y Parity Generator/Checkers y Code Converters y Priority Encoders y Decoder/Drivers for Display devices

Classification of Combinational Logic

The Analysis, Design and Optimization of Combinational Logic Circuit

Steps of Implementing Combinational Logic Circuit:

Working Principle of the Circuit: Problem Description Truth Table

Boolean Expression Boolean Algebra or postulate

Karnaugh Map

Simplified Boolean Expression

Logic Diagram

The Analysis, Design and Optimization of Combinational Logic Circuit

y Problem 01: There are two inputs and a single output. If both inputs

are same, output should be zero. Construct this circuit. y Solution: y A AB y B

A B  AB
A 0 0 1 1 B 0 1 0 1 Truth Table X
AB

0 1 1 0
AB

Logic Circuit

AB

The Analysis, Design and Optimization of Combinational Logic Circuit

y 1st Step: According to the problem description, we have drawn a truth

table. y 2nd Step: From the truth table, we have expressed the boolean expression as X ! A B  A B y 3rd Step: Given boolean expression is already in simplified form. So, no further simplification will be required. y 4th Step: From the simplified boolean expression, we have drawn the logic circuit and verified its operation.

The Analysis, Design and Optimization of Combinational Logic Circuit

y Problem 02: There are three inputs and one output. If two or more

inputs are high then output should be high. Construct the circuit. y Solution: A B C X
y y y

A B C X

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 0 1 1 1

A BC AB C ABC ABC

X ! ABC ABC  AB  ABC C

The Analysis, Design and Optimization of Combinational Logic Circuit A

B C X=AB+BC+CA

Simplification of Boolean expression:

X ! A BC  A B C  AB C  ABC ! BC ! BC ( A  A )  A B C  AB C  AB C  A B C

! B (C  A C )  A B C ! B ( C  A )( C  C )  A B C ! B (C  A )  A B C ! AB ! AB ! AB ! AB ! AB  BC  A B C  C (B  A B )  C ( B  A )( B  B )  C (B  A)  BC  CA

Combinational Arithmetic Circuits

y Addition: y Half Adder (HA). y Full Adder (FA). y Carry Ripple Adders. y Carry Look-Ahead Adders. y Subtraction: y Half Subtractor. y Full Subtractor. y Borrow Ripple Subtractors. y Subtraction using adders. y Multiplication: y Combinational Array Multipliers.

Half Adder
y Adding two single-bit binary values, X,Y produces a sum S bit and a carry out C-out bit. y This operation is called half addition and the circuit to realize it is called a half adder.

Half Adder Truth Table

Outputs Inputs

S(X,Y) = 7 (1,2) S = XY + XY S = X Y C-out(x, y, C-in) = 7 (3) C-out = XY

X Y

X 0 0 1 1
X Y

Y 0 1 0 1

S 0 1 1 0 Half Adder

C-out 0 0 0 1
S C-OUT

Sum S

C-out

Full Adder
y

Adding two single-bit binary values, X,Y with a carry input bit Sum S C-in produces a sum bit S and a carry out C-out bit.
XY C-in

00 0
0 1

01
2 3

11
6 7

10
4 5

Full Adder Truth Table

Inputs Outputs

1
C-in

X 0 0 0 0 1 1 1 1

Y 0 0 1 1 0 0 1 1

C-in 0 1 0 1 0 1 0 1

S 0 1 1 0 1 0 0 1

C-out 0 0 0 1 0 1 1 1

S = XY(C-in) + XY(C-in) + XY(C-in) + XY(C-in) S = X Y (C-in)

Carry C-out
XY C-in

00 0 1
0 1

01
2 3

11
6 7

10

1 1

4 5

1
Y

C-in

S(X,Y, C-in) = 7 (1,2,4,7) C-out(x, y, C-in) = 7 (3,5,6,7)

C-out = XY + X(C-in) + Y(C-in)

Full Adder Circuit Using AND-OR

X X X Y Y C-in C-in
X Y C-in X Y C-in X Y C-in X Y C-in XYC-in

XYC-in

Sum S

Y C-in

XYC-in

XYC-in

X Y

XY

C-out

Full Adder
S

C-in

X C-in Y C-in

XC-in

C-out

YC-in

Full Adder Circuit Using XOR

X Y C-in

Sum S

C-out

Full Adder
S

C-in
Y X C-in Y C-in

XY

XC-in

C-out

YC-in

n-bit Carry Ripple Adders

y An n-bit adder used to add two n-bit binary numbers can built by connecting in series n

full adders. y Each full adder represents a bit position j (from 0 to n-1). y Each carry out C-out from a full adder at position j is connected to the carry in C-in of the full adder at the higher position j+1. y The output of a full adder at position j is given by: Sj = Xj Yj Cj Cj+1 = Xj .Yj + Xj . Cj + Y . Cj
y In the expression of the sum Cj must be generated by the full adder at the lower position

j-1.
y The propagation delay in each full adder to produce the carry is equal to two gate delays

= 2(
y Since the generation of the sum requires the propagation of the carry from the lowest

position to the highest position , the total propagation delay of the adder is approximately: Total Propagation delay = 2 n(

4-bit Carry Ripple Adder

Inputs to be added

Adds two 4-bit numbers: X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the sum S = S3 S2 S1 S0 , C-out = C4 from the most significant position j=3

X3X2X1X0

Y3Y2Y1Y0

C4

C-out

4-bit Adder

C-in

C0 =0

Total Propagation delay

= 2 n( !8( or 8 gate delays

Data inputs to be added

S3 S2 S1 S0

Sum Output

X3

Y3
C3

X2

Y2
C2

X1

Y1
C1

X0

Y0

C4

C-out

Full Adder S3

C-in

C-out

Full Adder S2

C-in

C-out

Full Adder S1

C-in

C-out

Full Adder S0

C-in

C0 =0

Sum output

Larger Adders
y Example: 16-bit adder using 4, 4-bit adders y Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) producing a

16-bit Sum S (bits S0 to S15) and a carry out C16 from most significant position.
Data inputs to be added X (X0 to X15) , Y (Y0-Y15)
X3X2X1X0 Y3Y2Y1Y0 X3X2X1X0 Y3Y2Y1Y0 X3X2X1X0 Y3Y2Y1Y0 X3X2X1X0 Y3Y2Y1Y0

C16

C-out

4-bit Adder
S3 S2 S1 S0

C-in

C12

C-out

4-bit Adder
S3 S2 S1 S0

C-in

C8

C-out

4-bit Adder
S3 S2 S1 S0

C-in

C4

C-out

4-bit Adder
S3 S2 S1 S0

C-in

C0 =0

Sum output S (S0 to S15)

Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder = 4 x 2 n( ! x 8( !(
or 32 gate delays

Carry Look-Ahead Adders Looky The disadvantage of the ripple carry adder is that the propagation delay of adder (2 nD )

increases as the size of the adder, n is increased due to the carry ripple through all the full adders.
y Carry look-ahead adders use a different method to create the needed carry bits for each full

adder with a lower constant delay equal to three gate delays.

y The carry out C-out from the full adder at position i or Cj+1 is given by:

C-out = C i+1 = Xi . Yi + (Xi + Yi) . Ci

y By defining: y Gi = Xi . Yi as the carry generate function for position i

(one gate delay) (one gate delay)

(If Gi =1 C i+1 will be generated regardless of the value Ci)

y Pi = Xi + Yi as the carry propagate function for position i

(If Pi = 1 Ci will be propagated to C i+1)

y By using the carry generate function Gi and carry propagate function Pi , then C i+1 can be

written as: C-out = C i+1 = Gi + Pi . Ci

y To eliminate carry ripple the term Ci is recursively expanded and by multiplying out, we

obtain a 2-level AND-OR expression for each C i+1

Carry Look-Ahead Adders Looky For a 4-bit carry look-ahead adder the expanded expressions for all carry

bits are given by: C1 = G0 + P0.C0 C2 = G1 + P1.C1 = G1 + P1.G0 + P1.P0.C0 C3 = G2 + P2.G1 + P2.P1.G0 + P2.P1.P0.C0 C4 = G3 + P3.G2 + P3.P2.G1 + P3 . P2.P1.G0 + P3.P2.P1.P0.C0 where Gi = Xi .Yi Pi = Xi + Yi

y The additional circuits needed to realize the expressions are usually referred

to as the carry look-ahead logic. y Using carry-ahead logic all carry bits are available after three gate delays regardless of the size of the adder.

Ripple-carry adder, illustrating the delay of the carry bit.

4-bit CLA

The disadvantage of the carry-lookahead adder is that the carry logic is getting quite complicated for more than 4 bits. For that reason, carry-look-ahead adders are usually implemented as 4-bit modules and are used in a hierarchical structure to realize adders that have multiples of 4 bits. Figure 6 shows the block diagram for a 16-bit CLA adder. The circuit makes use of the same CLA Logic block as the one used in the 4-bit adder.

16-bit CLA Adder

Carry Look-Ahead Circuit Look-

Ci = Gi-1 + Pi-1. Gi-2 + . + Pi-1.P i-2. P1 . G0 + P i-1.P i-2. P0 . C0

Binary Arithmetic Operations Subtraction

y Two binary numbers are subtracted by subtracting each pair of

bits together with borrowing, where needed. y Subtraction Example: 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 0 0 1 1 0 Borrow 1 0 1

X 229 Y - 46 183

Half Subtractor
y Subtracting a single-bit binary value Y from anther X (I.e. X -Y ) produces a difference bit

D and a borrow out bit B-out.

y This operation is called half subtraction and the circuit to realize it is called a half

subtractor.

Half Subtractor Truth Table

Outputs

Inputs

D(X,Y) = 7 (1,2) D = XY + XY D = X Y B-out(x, y, C-in) = 7 (1) B-out = XY

X Y Difference D

X 0 0 1 1

Y 0 1 0 1

D 0 1 1 0

B-out 0 1 0 0

X Y

Half Subtractor

D B-OUT

B-out

Full Subtractor
y Subtracting two single-bit binary values,Y, B-in from

a single-bit value X produces a difference bit D and Difference D XY a borrow out B-out bit. This is called full subtraction.
B-in

00 0
0 1

01
2 3

11
6 7

10
4 5

Full Subtractor Truth Table

Inputs Outputs

1
B-in

X 0 0 0 0 1 1 1 1

Y 0 0 1 1 0 0 1 1

B-in 0 1 0 1 0 1 0 1

D 0 1 1 0 1 0 0 1

B-out 0 1 1 1 0 0 0 1

D = XY(B-in) + XY(B-in) + XY(B-in) + XY(B-in) S = X Y (C-in)

Borrow B-out
XY B-in

00 0 1
0 1

01
2 3

11
6 7

10
4 5

1 1
Y

B-in

S(X,Y, C-in) = 7 (1,2,4,7) C-out(x, y, C-in) = 7 (1,2,3,7)

B-out = XY + X(B-in) + Y(B-in)

Full Subtractor Circuit Using AND-OR

X X X Y Y B-in B-in
X Y B-in X Y B-in X Y B-in X Y B-in XYB-in

XYB-in

Difference D

Y B-in

XYB-in

XYB-in

X Y

XY

B-out

Full Subtractor
D

B-in

X B-in Y B-in

XB-in

B-out

YB-in

Full Subtractor Circuit Using XOR

X Y B-in

Difference D

B-out

Full Subtractor
D

B-in
Y X B-in Y B-in

XY

XB-in

B-out

YB-in

n-bit Subtractors
An n-bit subtracor used to subtract an n-bit number Y from another n-bit number X (i.e X-Y) can be built in one of two ways:
y By using n full subtractors and connecting them in series, creating a borrow

ripple subtractor:
y Each borrow out B-out from a full subtractor at position j is connected to the

borrow in B-in of the full subtracor at the higher position j+1.

y By using an n-bit adder and n inverters: y Find twos complement of Y by: y Inverting all the bits of Y using the n inverters. y Adding 1 by setting the carry in of the least significant position to 1 y The original subtraction (X -Y) now becomes an addition of X

to twos complement of Y using the n-bit adder.

4-bit Borrow Ripple Subtractor

Inputs
X3X2X1X0 Y3Y2Y1Y0

Subtracts two 4-bit numbers: Y = Y3 Y2 Y1 Y0 from X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the difference D = D3 D2 D1 D0 , B-out = B4 from the most significant position j=3

B4

B-out

4-bit Subtractor

B-in

B0 =0

D3 D2 D1 D0

Difference Output D

Data inputs to be subtracted X3 Y3

B3

X2

Y2
B2

X1

Y1
B1

X0

Y0

B4

B-out Full

B-in

B-out

Subtractor

B-in Full Subtractor

B-out Full

B-in

B-out

Subtractor

Full B-in Subtractor

B0 =0

D3

D2

D1 Difference output D

D0

4-bit Subtractor Using 4-bit Adder 4Inputs to be subtracted

Y3 Y2 Y1 X3 X2 X1 X0 Y0

C4

C-out

4-bit Adder
S3 S2 S1 S0

C-in

C0 = 1

D3

D2 D1

D0

Difference Output

Binary Multiplication
Multiplication is achieved by adding a list of shifted multiplicands according to the digits of the multiplier. y Ex. (unsigned)
y

11 X 13 -------33 11 ______ 143

X3 X2 X1 X0 x Y3 Y2 Y1 Y0 X 1101 multiplier (4 bits) __________________________ ------------------X3.Y0 X2.Y0 X1.Y0 X0.Y0 101 1 X3.Y1 X2.Y1 X1.Y1 X0.Y1 0000 X3.Y2 X2.Y2 X1.Y2 X0.Y2 X3.Y3 X2.Y3 X1.Y3 X0.Y3 1011 1011 P7 P6 P5 P4 P3 P2 P1 P0 --------------------10001111 Product (8 bits)

1011

multiplicand (4 bits)

_______________________________________________________________________________________________________________________________________________

y An n-bit X n-bit multiplier can be realized in combinational circuitry by using an

array of n-1 n-bit adders where is adder is shifted by one position. y For each adder one input is the multiplied by 0 or 1 (using AND gates) depending on the multiplier bit, the other input is n partial product bits.

4x4 Array Multiplier