Introduction to Sigma Delta

Converters
P.V. Ananda Mohan
Electronics Corporation of India
Limited,
Bangalore
How to reduce analog part?
Use Sigma-Delta Conversion
Front-end simple active RC Filter
SC/G
m
-C Sigma- Delta converter working at high
sampling frequency
Digital Decimation Filter using DSP
Scalable with digital technology
Only few OTAs or opamps, one comparator
needed, MOS switches needed
MODERN CODEC-FILTER

Active RC
Filter
input
SIGMA
-DELTA
Converter
Decimation
Digital
Filter
Digital
output
Over
sampling
Clock
Digital
Filter
clocks
What is sigma-delta conversion?
Similar to Delta Modulation but can code dc
(i.e.Slowly varying signals)
Generates One bit output sequence
Output word is obtained from this sequence by
finding the average using a decimator.
Also called Pulse density modulation
Also called over-sampled A/D conversion
High resolution up to 19 bits
Uses Oversampling and Noise shaping
Trades off accuracy in amplitude with accuracy in
time
Advantages
Analog part small area
Over sampling ratio typically 8 to 256.
Megahertz range up to 16 bits
Band-pass Sigma delta solutions are also
available.
First-Order Sigma Delta Modulator
+

-
+

-
I bit DAC
Integrator
Comparator
Difference
amplifier
V1
V
in
Vref
V2 Consider V
in
=0.2 volts and V
ref
=1 volt.
Number V
1
V
2
V
0
D
out
1 .2 .2 1 1
2 -.8 - .6 0 - 1
3 1.2 .6 1 1
4 - .8 - .2 0 - 1
5 1.2 1.0 1 1
6 -.8 .2 1 1
7 - .8 -.6 0 -1
8 1.2 .6 1 1
9 -.8 - .2 0 -1
Average of D
out
= (-1+1-1+1+1)/5 = 1/5 = 0.2

Result for 20 samples
Input volts Sequence of output bits
0.0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0.1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1
0.2 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1
0.7 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1
0.9 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
1.0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
V
o
(z)= V
i
(z)+e
n
.(1-z
-1
)

V
o
Two-loop Sigma-delta modulator
V
o
(z)=V
i
(z)+e
n
.(1-z
-1
)
2
Second order noise
shaping
+
Integrator
z
-1
/(1-z
-1
)
+
Integrator
z
-1
/(1-z
-1
)
comparator
latch
input
+
output
clock
2
Latch
Quantization noise of a linear
A/D
Difference between staircase and linear is a
triangular waveform.
A/2
-A/2
input
output
Linear models for Analysis
V
o
(z)= V
i
(z)+e
n
.(1-z
-1
)
Input low-pass and e
n
high-pass transfer
function; Shaping the Quantization noise!!!
+

-
+

-
I bit DAC
Integrator
Comparator
Difference
amplifier
V1
Ain
Vref
V2
e
n
Integrator
z
-1
/(1-z
-1
)
V
i
V
out
-
z
-1
Integrator or
Accumulator


Quantization noise for an A/D converter
12
. .
1
2
2 /
2 /
2 2
A
}
=
A
=
A
A
e e e
q q n
d
If peak to peak is FSR (Full scale range) , RMS
value is FSR

/(2\2).







02 . 6
76 . 1
) 76 . 1 02 . 6 ( 02 . 6 78 . 7 02 . 6
2
6
log . 20
2
6
2 2
12
12
2 2
12
2
2 2
2

=
+ = + =
|
|
.
|

\
|
=
= = =
A
=
SNR
ENOB
dB N N
FSR
FSR
SNR
N
dB
N N
N
RMS
SNR
V
Quantization noise of a Sigma
delta converter
Noise shaping function (1-z
-1
)
L
(1-z
-1
)
L
=

(1-e
-jT
)
L
= (e
-jT/2
)
L
.(e
jT/2
-e
-jT/2
)
L
|(1-z
-1
)
L
|

=

| (e
jT/2
-e
-jT/2
)
L
| = 2. Sin(f/f
s
)

= (2

f/f
s
)
L


( )
( ) ( )
1 2
.
12
.
1 2
.
12
.
12
1
1
2
2
1 2
1 2
2
2
2
2
2
2
1
+
=
+
=

=
A
|
|
.
|

\
|
A
}
A

+
+
=
L
s
L
s
df Noise
L
L
L
L
L
T ej z
L
s
f
f
f
f
z
f
t t
e
Candys Formula
( )
M
f
f
L
L
L
L
L
L
s
DR Range Dynamic
1 2
2
2
2
1 2
2
.
1 2
.
2
3
1 2
.
12
.
2 2
+
+
+
=
+
=
A
|
|
.
|

\
|
|
.
|

\
|
A
t
t
02 . 6
76 . 1
=
DRdB
ENOB


Advantages
(1-z
-1
)
L
has L zeros at dc
Signal and Quantization noise are treated
differently.
Output word is obtained from a sequence
of coarsely sampled input samples.
Analog part small area
Typical oversampling ratio 8 to 256.


For a Nyquist rate ADC DR
2
= 3.2
2B-1
For Second Order Sigma delta Converter,
16
.
5
.
2
3
5
4
t
= DR
16
.
7
.
2
3
7
6
t
= DR
M16, L=3
M=16, L=2
Ratio is 15.6 dB.
For M = 256, Ratio is ?????
Decimation filter
Occupies large area and consumes power.
Linear Phase FIR filter can be used.
Comb filters preferred since the input data
is one bit wide only.
Can Reduce sampling rate to four times the
Nyquist rate.
Lth order Noise shaping function, L+1th
order decimator is required.

Decimation filter
Local average can be computed efficiently
by by a decimator.
Frequency response
( )
( )
|
|
.
|

\
|
=
|
|
|
.
|

\
|

) sin(
) sin(
.
1
1
1
1
T
s
f
T
s
fD
D
z
z
D
k
k
t
t
Decimation filter
Decimation is reduction of sampling rate
Comb filters are used
Fixed coefficient FIR filters
One,Two or Three stages
Some designs use fixed coefficient IIR filters
Second order Sigma delta converter neds third-
order decimator filter.
Decimation filter example
input
output
clock
Accumulator
Latch
Input
Stream
Output
word
Lower
Clock
H(z) = (1-z
-64
)/(1-z
-1
)
DECIMATION FILTERS
Second order Decimator
H(z) = (1-z
-64
)
2
/(1-z
-1
)
2

Third-Order Decimator
H(z) = (1-z
-64
)
3
/(1-z
-1
)
3
Design is slightly involved-Three parallel
processors
Coefficient generation is dynamic for both
designs

ARCHITECTURES
ARCHITECTURES
Single stage Multiloop feedback
Multistage Noise Shaping (MASH)
Cascade Designs
Leslie-Singh Architecture
Fifth order single stage delta sigma
modulator

+ +
+
+
z
-1
/
(1-z
-1
)

z
-1
/
(1-z
-1
)

z
-1
/
(1-z
-1
)

z
-1
/
(1-z
-1
)


Q
z
-1
/
(1-z
-1
)
in
a
1
a
3
a
4
a
5
a
2

+
- - - -
-
Q Quantizer n bit Output
Fifth-Order Leap-Frog Sigma-Delta
Modulator

-
-
B2 b4
b5
a1 a2 a3 a4
a5
z
-1
/
(1-z
-1
)

z
-1
/
(1-z
-1
)

z
-1
/
(1-z
-1
)

z
-1
/
(1-z
-1
)

z
-1
/
(1-z
-1
)

ADC
DAC
OUT
b1 b3
b5
-
- -
-
IN
Single Loop Designs
No non linearity of DAC problems: only two
levels one and zero.
Quantization noise power is very high and hence
Need large over-sampling ratio
Single loop Sigma-delta modulators, gain
progressively increases and overloads the
comparator.
Delay also. Input change is felt after five stages.
High coefficient spread (large area)
Single Loop Designs
High coefficient sensitivity
Poor stability
All known digital filter structures cascade,
direct form, Leap frog can be used.
Single loop Sigma delta modulators reduce
integrator gin to achieve stability.


Multi stage noise shaping (MASH) Architecture
-
-
-
-
C1
X(z)
1/(1-z
-1
)
z
-1

Cpmparator
-
1/(1-z
-1
)
z
-1

Cpmparator
-
1/(1-z
-1
)
z
-1

Cpmparator
-
-
z
-1


C3
C2
z
-1


z
-1


MASH
Leakage is proportional to 1/A
v
2
Leakage is proportional to
C
2
MASH
Only last stage noise ideally remains.
Noise, distortion performance and Power
dissipation dependent largely on the first stage
leakage.
Digital Noise cancellation circuits.
Output is a word not a bit as in the case of Single
stage 1 bit A/D based design.
Complicates digital filters following the Analog
blocks.
Linear single bit Quantizer in the first stage
MASH needs to have low leakage, high opamp
gain 90dB low voltage applications not easily
realizable.

MASH
Leakage of Quantization noise from each
stage is because of the finite gain of the OA
Capacitor mismatch also leads to leakage.
Many versions available called as 1-1-1,1-
2-1, etc indicating the order of the loop in
each stage.
Upto fifth order modulators built.


Leslie-Singh Architecture
L(z)
N-bit
ADC
1/L(z)
1-bit
DAC

N N
1
N+1
+
-
L(z)
1-bit
ADC
H
1
(z)
1-bit
DAC

N N
1
N+1
+
-
N-bit
ADC
H
2
(z)
Leslie-Singh Architecture
This Architecture avoids matching problems of DAC
in first stage. Uses Two ADCs in effect.

1-bit
ADC
2z
-1
-z
-2
1-bit
DAC

N N
-
N+1
+
-
N-bit
ADC
(1-z
-1
)
2
Z
-1
Z
-1
Why Multi-bit Sigma delta
converters?
SNR can be improved by using multi-bit without
clocking fast, Candys formula
Problem of mismatch of resistors/capacitors
occurs
Nonlinearity of DAC is troublesome
Number of bits increases exponentially the
complexity (number of capacitors/resistors)
Typically restricted to 4 or 5 bits.
Can be used as single stage Multibit or one stage
of MASH
Bandpass Sigma Delta
Advantage immune to 1/f noise
No need for matching I and Q signals
Resonator
-
Input
Band-Pass Sigma delta
Modulator
H(z)=z
-2
and N(z)=(1+z
-2
)
2
Transmission
zeroes at f
s
/4, Obtained by z
-1
to z
-2

transformation.
z
-1
/
(1+z
-2
)
z
-1
/
(1+z
-2
)

Compara
tor
z
-1


z
-1

1 -1
1/2
X(z)
Y(z)
IMPLEMENTATION OPTIONS
Implementation Options
Switched Capacitor
OTA-C
Continuous-time
Combinations
SC Filters
SC solution
SC preferred because of accurate control of
integrator gains.
Fully Differential design increases signal
swing by two and dynamic range by 6dB.
Common mode signals such as supply lines,
substrate are rejected
Charges injected by switches are cancelled.
First integrator is important regarding noise,
linearity, settling behavior since second stage
Folded cascode Opamps recommended.
Nonidealities of comparator undergo noise
shaping and hence not very critical.
Comparator can be simple.
Capacitors chosen based on noise requirements.


Stray-Insensitive Inverting
Integrator
Vi
C1
C2
Vo
|1

|2
|1
|2
Stray-Insensitive Non-inverting Integrator
Vo
|1

|2
Vi
C1
C2
|1
|2
Typical Fully Differential SC
integrator
C
C 1d
2
_

+
Y YB
1
2
1
Y
YB
1d
V
REF+
V
REF-

V
REF-
V
REF+


Y

YB
2C
2C
Timing to avoid charge injection
1
2

1d
2d
Switch Implementation
Low ON resistance
Clock Feed-through (reduced by NMOS
transistor shunted by PMOS transistor)
Effect is to cause dc offset due to aliasing!

S
G
D
Inverter
Auto Zero-ed Integrator
Haug-Maloberti-Temes
Cancels noise, offset and finite gain effects
Output held over a clock period.
-


+
C2
C4
C3
C1
o
e
o
e
o
e
o
e
o
V
i
V
o
Switch Non-idealities
Fully-differential circuits recommended
Duplicated hardware; more area
Noise of switch due to ON resistance
kT/C noise, large capacitors need to be used for
low noise, noise independent of Switch ON
resistance R
on

Charging and discharging time dependent on
SC Sigma delta modulators OA of large
bandwidth at least five times the sampling
frequency and high gain are required.

COMPARATORS
Similar to OPAMPS but need logic level
outputs
Input referred offset of MOS
Opamps/comparators is quite high.
Offset compensation mandatory.
10 bit ADC with 1V signal, accuracy of a
comparator is 1mV. Thus, residual offset
has to be much smaller than 1mV.
A MOS comparator Combining gain
stage and latch
Out+
M
7
M
6

M
5

M
4

M
3

M
1
M
2

In-
V
B2

M
9

M
8

Out-
In+
V
B1

Strobe Strobe
bar
Typical Bipolar Comparator
Latch is a regenerative (positive feedback ) circuit
Input
V
out
CK
CKINV
Latch
Preamplifier
Flash Architectures for Multibit
Sigma delta converters
Quite fast
Number of comparators needed exponentially
increases with bit length.
Resistor ladders needed.
Usually 4 to 5 bit Flash A/D used to reduce
area.
Flash architecture
Comparators
input V
ref







Thermometer
code
Polysilicon
Resistor Ladder
Flash D/A converter Imperfections
Integral non-linearity
Differential non-linearity
Ac bowing due to input bias current drawn
by comparators.
Comparator kickback noise during transit
from latching to tracking

CT Sigma Delta Modulators

CT loop
filter

ADC
DAC
_ Input
CT Sigma Delta Modulators
Help to increase the clock frequency
Consume less power
OSR needs to be reduced for high bandwidth
applications.
No settling behavior problems.
Relaxed sampling networks
More sensitive to clock jitter
ADC jitter not much trouble
But DAC jitter troublesome. Since it is not noise
shaped
Non-zero excess loop delay


CT Sigma Delta Modulators
Large RC time constant variation
Mismatch between analog noise shaping and
digital noise shaping
CT Filters several alternative technologies
abvailable:
Active RC linear, not tunable
G
m
-C less power consumption,High frequency,
tunable
MOSFET-C non-linearity, advantage of tunability
First stage is very important
Mixture of Active RC ,G
m
-C used.
First stage Active RC for good linearity
Compensation capacitors not needed for
G
m
-C since integrator capacitor can
compensate the OTA
Sigma delta DAC
More tolerant to component mismatch and
circuit non-idealities
More digital
Keeping circuit noise low, and meeting
linearity are the challenges.
Sigma Delta DAC
Digital
Input

Interpolation
Digital Code
Conversion

0= 100000 =-1
1= 011111=+1

Digital
fiter
MSB
-VREF








-VREF
Analog
Low-
pass
filter
VREF
DAC
f
N
f
S

f
S
=M.f
N

f
S

f
S

Analog
Output
How to combat Nonlinearity of
DAC?
Capacitors/Resistors do have mismatch.
Randomize the mismatch.
In DWA, same set of DAC elements are used
cyclically and repeatedly under the guide of a
single pointer.
The element mismatch errors translate to tones at
the DAC output when the DAC input has a
periodic pattern.
DEM Logic must be optimized for low delay.
DEM
Flash output Thermometer code
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 =5
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 =9
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 =3
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 =12


-
+
C
C

C
C
Sixteen capacitors
1
2

15
16
x x x x X
x x x x x x x x x
x x x
x x x x x x x x x x x x
Power Dissipation
Settling performance of the Opamp decides
g
m
.
Power dissipation is dependent on bias
current which is decided by G
m
.
General Guidelines
Stability (Overload)
Long strings of ones or zeroes are detected and
reset is given to integrators to improve stability.
Stabilization techniques needed e.g. clamping of
integrator outputs.
Extensive simulation needed e.g Matlab Sigma
Delta Tool Box R.Schrier
Rules of Thumb
Maximum of Magnitude of H(z) shall be <1.5
(Lees rule)
More relaxed designs available now: Magnitude of
H(z) up to 6.
Idle tones in band
General Guidelines
Thumb rule GB of OA > 2.5F
S
Switch resistances can be as low as 150 Ohms.
Offset of Comparator <10mV
Hysteresis of comparator <20mV
Single stage modulators are quite tolerant of
nonidealities
Instability means that large not necessarily
unbounded states gives poor SNR compared to
linear models.
Reducing OBG (Out of band gain) improves
stability
Capacitors with low voltage coefficients ensure
good linearity.
General Guidelines
OPamps with large dc gain in first stage.
Cancellation of even harmonics feasible by
fully differential circuits
Top plates of capacitors to virtual grounds
of Opamps
Full switches parallel NMOS and PMOS for
input whereas only NMOS for those feeding
virtual ground.
General Guidelines
Comparator metastability
Effect of clock jitter is independent of the
order or structure of the modulator.
Clock A cos(
o
t) becomes due to jitter A
cos(
o
(t+Sin(t)).This adds to the input
and sidebands are formed:
o
+ , and
o
- )
of amplitude A
o
/2
SNR is affected by A
2

o
2
/2


Sigma Delta Frequency Synthesizer
Frequency
reference
Multimodulus
frequency divider
VCO Loop Filter Phase
Detector
Sigma-Delta
Modulator
Precompensation
Filter
Gaussian
Filter
Data
Sequence
Conclusion
More than 400 papers
IEEE press books
Simulation tools
Months of simulation may be needed to
weed out problems.
Several solutions
Applications emerging for 802.11, Blue
Tooth, CDMA/GSM/3G handsets
Contact
anandmohanpv@hotmail.com
pvam@vsnl.net
Thank You