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B.
Supmonchai
2102-545 Digital ICs SPICE Simulations 1
MOSFET Models
Earlier SPICE versions had three built-in
MOSFET models:
LEVEL 1 (MOS1) - Square law I-V characteristic
LEVEL 2 (MOS2) - Detailed analytical MOSFET
LEVEL 3 (MOS3) - Semi-empirical
MOS2 and MOS3 include second-order effects
such as velocity saturation, mobility
degradation, subthreshold conduction, and
DIBL.
All three LEVELs do not provide good fits to
the characteristics of modern devices.
B.Supmonchai
MOSFET Models (2)
For modern submicron devices, the Berkeley
Short-Channel IGFET Model (BSIM) is the most
widely used (commercially and academically).
BSIM version 1, 2, 3v3, and 4 are implemented as
SPICE level 13, 39, 49, and 54, respectively
BSIM is a very elaborate model that are derived
from the underlying device physics but use an
enormous number of parameters to fit the behavior
of modern transistor.
BSIM version 3v3 requires over 27 pages of over 100
parameters and device equations to describe the model.
B.Supmonchai
Selection of Models
The level (type) of MOSFET model to be used
in a particular simulation can be specified
through the .MODEL statement in SPICE.
With the statement, the user can describe a large
number of model parameters including geometry
of the device such as channel length and width.
M1 3 1 0 0 NMOD L=1U W=10U AD=120P PD=42U
MDEV32 14 9 12 5 PMOD L=1.2U W=20U
.MODEL NMOD NMOS (LEVEL=1 VTO=1.4 KP=4.5E-5 CBD=5PF CBS=2PF)
.MODEL PMOD PMOS (VTO=-2 KP=3.0E-5 LAMBDA=0.02 GAMMA=0.4
+ CBD=4PF CBS=2PF RD=5 RS=3 CGDO=1PF
+ CGSO=1PF CGBO=1PF)
B.Supmonchai
NMOS Transistor Circuit Model
B.Supmonchai
LEVEL 1 Model Equations
Corresponding to our unified model for manual
analyses in the class.
Basic Current Models:

I
DS
=

0 V
GS
<V
T
cutoff
k'
W
eff
L
eff
1+ V
DS
( )
V
GS
V
T

V
DS
2
|
\

|
.
|
V
DS
V
DS
<V
GS
V
T
linear
k'
2
W
eff
L
eff
1+ V
DS
( )
V
GS
V
T
( )
2
V
DS
>V
GS
V
T
saturation

V
t
=V
T 0
+ 2|
F
V
SB
2|
F ( )
where
B.Supmonchai
LEVEL 1 Model Equations (II)
Completely characterized by the five electrical
parameters: k, V
T0
, , |2|
F
|, and (KP, VTO,
GAMMA, PHI, and LAMBDA in SPICE)
Physical parameters, e.g., t
ox
(TOX) can be specified
in stead of the electrical parameters.
If both present simultaneously in the model,
electrical parameters always override physical
parameters.
Though grossly inaccurate, LEVEL 1 offers a
quick, useful estimate of the circuits.
B.Supmonchai
LEVEL 2 and 3 Model Equations
Improved models for the drain current
Level 2: A number of semi-empirical corrections
have been added to the basic equations.
Level 3: Majority of the model equations are
empirical
Improving accuracy
Reducing complexity in calculation.
Although more accurate, LEVEL 2 and 3
models are still insufficient to achieve good
agreement with experimental data for the deep
submicron devices.
B.Supmonchai
Parasitic Capacitances
SPICE models use separate sets of equations in
cut-off, linear, and saturation modes to calculate
the device parasitic capacitances.
Gate Capacitances: SPICE uses a simple model
that represents the charge storage effect by three
nonlinear two-terminal capacitors: C
GB
, C
GS
, and
C
GD
(please see chapter 2 for the detail)
Required geometry information: gate oxide thickness
(TOX), channel width (W), channel length (L), and
the lateral diffusion (LD).
B.Supmonchai
Parasitic Capacitances (2)
Junction Capacitance: SPICE uses the simple
pn-junction model to simulate the parasitic
capacitances of the source and drain diffusion
regions.

C
SB
=
C
j
AS
1+
V
SB
|
0
|
\

|
.
|
M
j
+
C
jsw
PS
1+
V
SB
|
0
|
\

|
.
|
M
jsw
C
DB
=
C
j
AD
1+
V
DB
|
0
|
\

|
.
|
M
j
+
C
jsw
PD
1+
V
DB
|
0
|
\

|
.
|
M
jsw
where AS and AD are the source and the drain areas; PS and
PD are the source and the drain perimeters, respectively
B.Supmonchai
Parasitic Capacitances (3)
C
j
is the zero-bias depletion capacitance per unit area at
the bottom plate of the drain or the source diffusion
region. (CJ in SPICE)
C
jsw
is the zero-bias depletion capacitance per unit length
at the side-wall plate. (CJSW)
M
j
and M
jsw
are the junction degrading coefficients of the
bottom and side-wall plates, respectively. (MJ, MJSW)
0.5 for abrupt juction and 0.33 for linearly graded junction
|
0
is the built-in junction potential which is actually a
function of the doping densities (PB for bottom plate
and PHP (MOS) or PBSW (BSIM) for side walls)
B.Supmonchai
Example: NMOS I-V Characteristics
* mosiv.sp

*------------------------------------------------
* Parameters and models
*------------------------------------------------
.include '../models/tsmc180/models.sp'
.temp 70
.option post

*------------------------------------------------
* Simulation netlist
*------------------------------------------------
*nmos
Vgs g gnd 0
Vds d gnd 0
M1 d g gnd gnd NMOS W=0.36u L=0.18u

*------------------------------------------------
* Stimulus
*------------------------------------------------
.dc Vds 0 1.8 0.05 SWEEP Vgs 0 1.8 0.3
.end
V
gs
V
ds
I
ds
4/2
B.Supmonchai
Example: I-V Characteristics
V
ds
0.0 0.3 0.6 0.9 1.2 1.5 1.8
I
ds
(A)
0
50
100
150
200
250
V
gs
= 1.8
V
gs
= 1.5
V
gs
= 1.2
V
gs
= 0.9
V
gs
= 0.6
B.Supmonchai
Example: Inverter Transient Analysis
inv.sp

*------------------------------------------------
.param SUPPLY=1.8
.option scale=90n
.temp 70
.option post

*------------------------------------------------
Vdd vdd gnd 'SUPPLY'
Vin a gnd PULSE 0 'SUPPLY' 50ps 0ps 0ps 100ps 200ps
M1 y a gnd gnd NMOS W=4 L=2
+ AS=20 PS=18 AD=20 PD=18
M2 y a vdd vdd PMOS W=8 L=2
+ AS=40 PS=26 AD=40 PD=26

* Stimulus
*------------------------------------------------
.tran 1ps 200ps
.end
a
y
4/2
8/2
**Unloaded inverter**
B.Supmonchai
Example: Inverter Transient Results
(V)
0.0
1.0
t(s)
0.0 50p 100p 150p 200p
v(a)
v(y)
t
pdr
= 15ps t
pdf
= 12ps
t
f
= 10ps
t
r
= 16ps
0.36
1.44
1.8
Overshoot
Very fast
edges
B.Supmonchai
Subcircuits
Common elements can be declared as subcircuits
SPICE Decks are easier to read and maintain.
.subckt inv a y N=4 P=8
M1 y a gnd gnd NMOS W='N' L=2
+ AS='N*5' PS='2*N+10' AD='N*5' PD='2*N+10'
M2 y a vdd vdd PMOS W='P' L=2
+ AS='P*5' PS='2*P+10' AD='P*5' PD='2*P+10'
.ends
a b c d e
X1 X2 X3 X4
1
2
4
8
16
32
64
128
f
X5
256
512
Shape input
Device
Under
Test Load
Load on
Load
Ex: Fanout-of-4 Inverter Delay
Reuse inv
Shaping
Loading
B.Supmonchai
Example: FO4 Inverter Delay
* fo4.sp

*----------------------------------------------------------------------
.param SUPPLY=1.8
.param H=4
.option scale=90n
.temp 70
.option post

* Subcircuits
*----------------------------------------------------------------------
.global vdd gnd
.include '../lib/inv.sp'

*----------------------------------------------------------------------
Vdd vdd gnd 'SUPPLY'
Vin a gnd PULSE 0 'SUPPLY' 0ps 100ps 100ps 500ps 1000ps
X1 a b inv * shape input waveform
X2 b c inv M='H' * reshape input waveform

B.Supmonchai
Example: FO4 Inverter Delay (2)
X3 c d inv M='H**2' * device under test
X4 d e inv M='H**3' * load
x5 e f inv M='H**4' * load on load

* Stimulus
*----------------------------------------------------------------------
.tran 1ps 1000ps
.measure tpdr * rising prop delay
+ TRIG v(c) VAL='SUPPLY/2' FALL=1
+ TARG v(d) VAL='SUPPLY/2' RISE=1
.measure tpdf * falling prop delay
+ TRIG v(c) VAL='SUPPLY/2' RISE=1
+ TARG v(d) VAL='SUPPLY/2' FALL=1
.measure tpd param='(tpdr+tpdf)/2' * average prop delay
.measure trise * rise time
+ TRIG v(d) VAL='0.2*SUPPLY' RISE=1
+ TARG v(d) VAL='0.8*SUPPLY' RISE=1
.measure tfall * fall time
+ TRIG v(d) VAL='0.8*SUPPLY' FALL=1
+ TARG v(d) VAL='0.2*SUPPLY' FALL=1
.end
B.Supmonchai
Example: FO4 Inverter Delay Results
(V)
0.0
0.5
1.0
1.5
2.0
t(s)
0.0 200p 400p 600p 800p 1n
a
b
c
d
e
f
t
pdf
= 66ps t
pdr
= 83ps
B.Supmonchai
Device Characterization
Modern SPICE models are so complicated that
the designer cannot easily read key performance
characteristics from the model files.
A more convenient approach is to run a set of
simulations and then extract parameters and
other interesting data, e.g., I-V characteristics,
threshold voltage, effective resistance and
capacitance.
Various methods to find these parameters and the
required simulations are described in the literature.
B.Supmonchai
Device Characteristics Comparison
B.Supmonchai
Pitfalls and Fallacies
Failing to estimate diffusion and interconnect parasitics
in simulations
Diffusion capacitance can account for more than 50% of the
delay of a high fan-in, low fanout gate. Make sure that the area
and perimeter of the source and drain are included in the
simulation.
RC delay of the long wires dominate the path delay but it is
difficult to estimate.
Good models describe not only the circuit but also the
input edge rates, the output loading, and parasitics such
as diffusion capacitance and interconnect.
Gate delay is strongly dependent on the rise/fall time of the
input and even more strongly on the output loading
B.Supmonchai
Pitfalls and Fallicies (2)
SPICE is prone to Garbage in, Garbage out! So
do not blindly trust the results from SPICE.
Failing to account for hidden scale factors
Identifying incorrect critical path
Choosing inappropriate transistor sizes
Compare results of a design with carefully selected
transistor sizes to a convention design with poorly selected
sizes.
Do not use SPICE in place of thinking
Do not use SPICE too much. Circuit simulation
should be guided by analysis
B.Supmonchai
Pitfalls and Fallacies (3)
Rule of Thumbs:
Assume SPICE decks are buggy until proven otherwise.
If the simulation does not agree with your
expectations, look closely for errors or inadequate
modeling in the deck.
Motto: Check and Recheck!

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