WELCOME TO THE SEMINAR ON

3- D ICs
by JINS JOSEPH

Introduction
3-D ICs are an attractive chip architecture that can alleviate the interconnect related problems such as delay and power dissipation and can also facilitate integration of heterogeneous technologies in one chip (SoC). The multi-layer chip industry opens up a whole new world of design. With the Introduction of 3-D ICs, the world of chips may never look the same again In the 3-Ddesign architecture, an entire chip is divided into a number of blocks, and each block is placed on a separate layer of Si that are stacked on top of each other.

Motivation for 3-D ICs

Interconnect limited VLSI performance Physical limitations of cu interconnects System on a chip design

3D Architecture

Advantages of 3D architecture
Small size, weight and cost. High reliability. Low power consumption Improved performance Fast operation

Limitations
Functions at fairly low voltage Limited power dissipation Difficult to achieve low noise and high voltage operation Poor high frequency performance Capacitors and resistors have lower maximum values

Area and performance estimation of 3D ICs

Rents Rule
T=kNP -------------(i)

2-D and 3-D Wire-length distributions

I(l)= i(x)dx -----------(ii)

Estimating 2-D and 3-D chip area

Arequired = Ac (PlocLtotal_loc+PsemiLtotal_semi+PglobLtotal_glob)/N

 Two Active Layer 3-D Circuit Performance

Chip area minimization with fixed interconnect delay Increasing Chip Area and Performance

Effect of Increasing Number of Silicon Layers Effect of Increasing the Number of Metal Layers Optimization of Interconnect Distribution

Challenges for 3-D Integration

Thermal issues in 3-D ICS Reliability issues in 3-D ICS

Overview OF 3-D IC Technology

Beam recrystalization

 Silicon Epitaxial Growth

 Processed wafer bonding Solid phase crystallization (SPC) Vertical interlayer interconnect technology options

Advantages
The 3D chip design technology can be exploited to build SoCs by placing circuits with different voltage and performance requirements in different layers The 3D integration can reduce the wiring, thereby reducing the capacitance, power dissipation and chip area and therefore improve chip performance Additionally the digital and analog components in the mixed-signal systems can be placed on different Si layers thereby achieving better noise performance due to lower electromagnetic interference between such circuits blocks

APPLICATIONS
Portable electronicsdigital cameras ,digital audio players, PDAs One of the largest constraints to growth has been affordable storage, creating the marketing opportunity for ultra low cost internal and external memory. Device designers often trade application richness to meet tight cost targets of existing mask ROM and NAND flash non volatile technology

Conclusion
The 3 D memory will just the first of a new generation of dense, inexpensive chips that promise to make digital recording media both cheap and convenient enough to replace the photographic film and audio tape. We can understand that 3-D ICs are an attractive chip architecture, that can alleviate the interconnect related problems such as delay and power dissipation and can also facilitate integration of heterogeneous technologies in one chip. The multilayer chip building technology opens up a whole new world of design like a city skyline transformed by skyscrapers, the world of chips may never look at the same again.

References
Jose E Schutt-Aine , sung-Mo Kang,Interconnections addressing the next challenge of IC technology at page 583 Robert h Have Mann, James A Hutch by,High performance interconnects: an integration overview at page 586. Kaustav Banerjee, Shukri J Souri, Pawan Kapur and Krishna C Sara swath 3-D ICs: a novel chip design for improving deep sub micrometer interconnect performance and Soc integration at page 602.

Thank You