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CMOS Fabrication

n-substrate

CMOS inverter: (a) circuit diagram; (b) layout; and (c) cross section

In the processing, a p-tub (also called a p-well) is first implanted and subsequently driven into the n-substrate. The p-type dopant concentration must be high enough to overcompensate the background doping of the n-substrate. The subsequent processes for the n-channel MOSFET in the p-tub are identical to those described previously.

Various CMOS structures:

Instead of the p-tub described above, an alternate approach is to use an n-tub formed in p-type substrate, as shown in Figure (d). In this case, the n-type dopant concentration must be high enough to overcompensate for the background doping of the p-substrate (i.e., ND > NA).

(d) n-tub

(e) twin-tub

In both the p-tub and the n-tub approaches, the channel mobility will be degraded because mobility is determined by the total dopant concentration (NA + ND). A more recent approach using two separated tubs implanted into a lightly doped substrate is shown in Figure (e). This structure is called a twin tub. Because no overcompensation is needed in either of the twin tubs, higher channel mobility can be obtained.

All CMOS circuits have the potential for a problem called latchup that is associated with parasitic bipolar transistors.These parasitic devices consist of the npn transistor formed by the NMOS sourcedrain regions, p-tub, and n-type substrate, the pnp transistor formed by the PMOS source-drain regions,n-type as well as substrate, and p-tub. Under appropriate conditions, the collector of the pnp device supplies base current to the npn and vice versa in a positive feedback arrangement. This latchup current can have serious negative repercussions in a CMOS circuit.

(f) refilled trench

An effective processing technique to eliminate latchup is to use deep-trench isolation, as shown in Figure (f). In this technique, a trench with a depth deeper than the well is formed in the silicon by anisotropic reactive sputter etching. An oxide layer is thermally grown on the bottom and walls of the trench, which is then refilled by deposited polysilicon or silicon dioxide. This technique can eliminate latchup because the

Fabrication steps of a trench isolation: An example is shallow trench (depth less than 1m) isolation, shown in Figure (G).

Figure G . Shallow-trench isolation: (a) patterning on nitrideoxide films; (b) dry etching and chanstop implantation; (c) CVD oxide to refill; (d) surface after CMP.

After patterning (Figure a), the trench area is etched (Figure b) and then refilled with oxide using chemical vapor deposition (CVD), (Figure c). Since the oxide has overfilled the trench,the oxide on the nitride should be removed. Chemicalmechanical polishing(CMP) is used to remove the oxide on the nitride and to get a flat surface (Figure d).

BiCMOS Fabrication
BiCMOS technology: BiCMOS is a technology that combines both CMOS and bipolar device structures in a single IC. The reason to combine these two different technologies is to create an IC chip that has the advantages of both CMOS and bipolar devices. We know that CMOS exhibits advantages in power dissipation, noise margin, and packing density, whereas bipolar technology shows advantages in switching speed, current drive capability, and analog capability. As a result, for a given design rule, BiCMOS can have a higher speed than CMOS, better performance in analog circuits than CMOS, a lower power dissipation than bipolar, and a higher component density than bipolar .BiCMOS has been widely used in many applications. Early on, it was used in static random access memory (SRAM) circuits. Currently, BiCMOS technology has been successfully developed for transceiver, amplifier, and oscillator applications in wireless communication equipment. BiCMOS Processing Steps: Most BiCMOS processes are based on standard CMOS process with some modifications, such as adding masks for bipolar transistor (BJT) fabrication.

BJT in n-wall CMOS process:

Figure (F) BiCMOS device structure

The example shown in Figure (F) is for high-performance BiCMOS process based on the twin-well CMOS approach. The initial material is a p-type silicon substrate. An n+ buried layer is formed to reduce collector resistance. The buried p layer is formed by ion implantation. A lightly doped n-epi layer is grown on the wafer, and a twin-well process for the CMOS is performed. To achieve high performance for the bipolar transistor, four additional masks are needed: 1-the buried n+ mask, 2-the collector deep n+ mask, 3-the base p mask, and 4-the polyemitter mask. The p+ region for base contact can be formed with the p+ implant in the source-drain implantation of the PMOS, and the n+ emitter can be formed with the source-drain implantation of the NMOS. The additional masks and longer processing time compared with a standard CMOS process are the main drawbacks of BiCMOS.

BiCMOS npn transistor : The basic process steps used are those already outlined for CMOS but with additional process steps and additional masks defining: (i) the p +base region; (ii) n +collector area; and (iii) the buried sub collector. Theoretically there should be little difficulty in extending CMOS fabrication processes to include bipolar as well as MOS transistors. In fact, a problem of p-well and n-well CMOS processing is that parasitic bipolar transistors are inadvertently formed as part of the outcome of fabrication (see CMOS latchup section).

Production of npn bipolar transistors with good performance characteristics can be achieved, e.g., by extending the standard n-well CMOS processing to include further masks to add two additional layers; the n+ subcollector and p+ base layers.
The npn transistor is formed an n-well & the additional p+ base region is located in the well to form the p-base region of the transistor. The second additional layer, the buried n+ subcollector is added to reduce the n-well (collector) resistance & thus improve the quality of the bipolar transistor.

Plan view & Cross-section of BiCMOS npn transistor

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