Hardware Practicals

8255 Programmable Peripheral Interface

8255 Basics

8255 Structure
The 8255 has 24 input/output pins in all. These are divided into three 8-bit ports. Port A and port B can be used as 8-bit input/output ports. Port C can be used as an 8-bit input/output port or as two 4-bit input/output ports or to produce handshake signals for ports A and B. The three ports are further grouped as follows: Group A consisting of port A and upper part of port C. Group B consisting of port B and lower part of port C. Eight data lines (D0 - D7) are available (with an 8-bit data buffer) to read/write data into the ports or control register under the status of the "RD" (pin 5) and WR" (pin 36), which are active low signals for read and write operations respectively. The address lines A1 and A0 allow to successively access any one of the ports or the control register as listed below:

Address Line Decoding

CS 0 A1 0 A0 0 Selection port A 0 0 1 port B

port C

Control Register

8255 is disabled

Operational Modes
Operational modes of 8255 There are two main operational modes of 8255: Input/output mode Bit set/reset mode

Input Output Mode

Mode 0: In this mode, the ports can be used for simple input/output operations without handshaking O/p are latched. I/p are buffered not latched. Port do not have handshake or interrupt capability. Mode 1 When we wish to use port A or port B for handshake (strobed) input or output operation, we initialise that port in mode 1 (port A and port B can be initilalised to operate in different modes, For port B in this mode (irrespective of whether is acting as an input port or output port), PC0, PC1 and PC2 pins function as handshake lines. Mode 2 Only group A can be initialised in this mode. Port A can be used for bidirectional handshake data transfer

Control Word

An analog-to-digital converter
Write 8086 ALP to convert an analog signal in the range of 0V to 5V to its corresponding digital signal using successive approximation ADC. Find resolution used in both the ADC's and compare the results.

Allocation of Ports for 8255

WE USE PORT A,C AS INPUT AND B AS OUTPUT A READING ADC DATA (Actual Value) I/P B CONTROL SIGNALS (SOC/OE/CLK) O/P C STATUS SIGNALS (EOC) I/P
d7
1

d6
0

d5
0

d4
1

d3
1

d2
0

d1
0

d0
1

I/O mode

Group A Mode 0

Port Port C Upper a

Mode Port B Selecti (o/P) on PB/C

Port C Lower (1=I/P)

Circuit Diagram
B0 = SOC B1=OE B2=CLK B0
D 0 D 7 S T A R T

67 8255 Control Word 61 Port A 63 Port B 65 Port C

C L K

O E

E O C

B2

B1 C1

Process for ADC

Code
0000:1000 0000:1002 0000:1004 0000:1006 0000:1008 0000:100A 0000:100C 0000:100E 0000:1010 0000:1012 0000:1014 0000:1016 0000:1018 MOV AL, 99 OUT 67, AL MOV AL, 05 OUT 63, AL MOV AL, 04 OUT 63, AL IN AL, 65 AND AL, 01 JZ 100C MOV AL, 06 OUT 63, AL IN AL, 61 INT 3 ; Control word 8255 ;Ports allocated in I/o ;Port B Control Word ;SOC and CLK high ;Port B Control Word ;CLK LOW SOC high ;Status word in mem ;Check for EOC ;Else wait in loop C0 - EOC B0 = SOC ;Clk and OE B1=OE ; B2=CLK 67 8255 ;Actual Value Control Word ;End
61 Port A 63 Port B 65 Port C

Part II DAC 0809

A DAC converts an abstract finite-precision number (usually a fixed-point binary number) into a concrete physical quantity (e.g., a voltage or a pressure). In particular, DACs are often used to convert finiteprecision time series data to a continually varying physical signal.

Terms
Resolution: This is the number of possible output levels the DAC is designed to reproduce. This is usually stated as the number of bits it uses, which is the base two logarithm of the number of levels. For instance a 1 bit DAC is designed to reproduce 2 (21) levels while an 8 bit DAC is designed for 256 (28) levels. Resolution is related to the effective number of bits (ENOB) which is a measurement of the actual resolution attained by the DAC. Maximum sampling frequency: This is a measurement of the maximum speed at which the DACs circuitry can operate and still produce the correct output. As stated in the NyquistShannon sampling theorem, a signal must be sampled at over twice the frequency of the desired signal. For instance, to reproduce signals in all the audible spectrum, which includes frequencies of up to 20 kHz, it is necessary to use DACs that operate at over 40 kHz. The CD standard samples audio at 44.1 kHz, thus DACs of this frequency are often used. A common frequency in cheap computer sound cards is 48 kHz many work at only this frequency, offering the use of other sample rates only through (often poor) internal resampling.

Structure of D to A
Ports A and B are defined in Output mode and port C in input mode The 8 bit data i/p is written into Port A by CPU
A0-A7 A0-A7

Data Latch

D to A converter

This data is latched by a positive latch pulse through PB0 of port B used as CONTROL PORT When reset is pressed the address and data bus of 8255 are tristated and logic 1 in Latch remains in flow condition DAC gets FF as hex input and gives full scale o/p

Allocation of Ports for 8255

WE USE PORT A,C AS INPUT AND B AS OUTPUT A GIVING DAC DATA (Actual Value) O/P B CONTROL SIGNALS (SOC/OE/CLK) O/P C STATUS SIGNALS (EOC) I/P
d7
1

d6
0

d5
0

d4
0

d3
1

d2
0

d1
0

d0
1

I/O mode

Group A Mode 0

Port Port C Upper a

Mode Port B Selecti (o/P) on PB/C

Port C Lower (1=I/P)

RAMP
0000:1000 MOV AL,89 0000:1002 OUT 67,AL 0000:1004 MOV AL,01 0000:1006 OUT 63,AL 0000:1008 MOV AL,00 0000:100A OUT 61,AL 0000:100C INC AL 0000:100E JMP 100A ;Control Word 8255 ;Write ;Set port B Latch as 1 ;Latch it in ;start value ;Port A (Giving Digital) ;Increment AL by 1 ;Output again

Triangular
0000:1000 MOV AL,89 0000:1002 OUT 67,AL 0000:1004 MOV AL,01 0000:1006 OUT 63,AL 0000:1008 MOV AL,00 0000:100A INC AL 0000:100C OUT 61,AL 0000:100E CMP AL,FF 0000:1010 JNE 100A 0000:1012 DEC AL 0000:1014 OUT 61,AL 0000:1016 CMP AL,00 0000:1018 JNE 1012 0000:101A JMP 1008 0000:101C INT 3

Square
0000:1000 MOV AL,89 0000:1002 OUT 67,AL 0000:1004 MOV AL,01 0000:1006 OUT 63,AL 0000:1008 MOV CL,FF 0000:100A MOV AL,00 0000:100C OUT 61,AL 0000:100E DEC CL 0000:1010 JNZ 100E 0000:1012 MOV CL,FF 0000:1014 MOV AL,FF 0000:1016 OUT 61,AL 0000:1018 DEC CL 0000:101A JNZ 1018 0000:101C JMP 100A 0000:101E INT 3

8253
The Intel 8253 and 8254 are Programmable Interval Timers (PITs), which perform timing and counting functions The 8253/54 solves one of most common problem in any microcomputer system,the generation of accurate time delays under software control. Instead of setting up timing loops in system software, the programmer configures the 8253/54 to match his requirements, initializes one of the counters of the 8253/54 with the desired quantity, then upon command the 8253/54 will count out the delay and interrupt the CPU when it has completed its tasks. It is easy to see that the software overhead is minimum and that multiple delays can be easily be maintained by assignment of priority levels.

Difference between 53/54

Data Bus buffer and RD/WR

Control Word
D7 D6 D5 D4 D3 D2 D1 D0

SC1

SC0

RW1

RW0

M2

M1

M0

BCD

Eg Mode 0 0
M2 0 0 X X 1 1 M1 0 0 1 1 0 0

1
M0 0 1 0 1 0 1

0
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5
RW1

0
BCD
0 1

Binary Counter 16-bits BCD Counter (4 Decades)

RW0 0 1 0 1 Counter Latch Command Read/Write LSB only Read/Write MSB only Read/Write LSB first, then MSB

SC1

SC0 0

0 0 1 1

0 1 0 1

Select Counter 0 Select Counter 1 Select Counter 2 Read-Back Command

0 1 1

Modes
Mode 0
Set Output Bit when timer done (Interrupt on terminal count) The output will start off zero. The count is loaded and the timer will start to count down. When the count has reached zero the output will be set high, and remain high until the next count has been reloaded.

First HIGH, then at next negative clock edge goes LOW, then finishes HIGH
Mode 1: Programmable One-Shot The output will go low following the rising edge of the gate input. The counter will count and the output will go high once the counter has reached zero.

Other Modes
Mode 2: Rate Generator The counter will continually count down, when the count reaches zero, the output will pulse low and the counter will be reloaded. Mode 3: Square Wave Generator This mode is similar to Mode 2 except the output remains low for half of the timer period and high for the other half of the period. Mode 4: Software Triggered Pulse The output will remain high untill the timer has counted to zero, at which point the output will pulse low and then go high again. Mode 5: Hardware Triggered Pulse The counter will start counting once the gate input goes high, when the counter reaches zero the output will pulse low and then go high again.

Mode 0

Mode 0 Diagram
Interrupt on Terminal Count Assume GATE=1 (HIGH) When data LSB is loaded, it is transferred to counter on next ve clock edge, starting the counter When counter reaches 0 , OUT0 pin goes high If gate becomes low inbetween counter suspends counting If new count loaded, that count is used and decremented to zero

Mode 1 Diagram

Mode 2

Mode 3

33 Control Word (Counter Port) Counter 0 30H Counter 1 31H Counter 2 32H

Mode 0
;Counter 0 LSB then MSB (b) ;Loading LSB first ;Loadin MSB (16 bit) ;Counter LATCH ;Specific latch for mode 0 ;Get counter 1LSB contents ;Move to DL ;Get counter 1MSB ;Move to DH ;End

Dyna-86>U 2000 0000:2000 MOV AL, 30 0000:2002 OUT 33, AL 0000:2004 MOV AL, 05 0000:2006 OUT 30, AL 0000:2008 MOV AL, 00 0000:200A OUT 30, AL 0000:200C MOV AL, 00 0000:200E OUT 33, AL 0000:2010 IN AL, 30 0000:2012 MOV DL, AL 0000:2014 IN AL, 30 0000:2016 MOV DH, AL 0000:2018 INT 3

8251
The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data communication. As a peripheral device of a microcomputer system, the 8251 receives parallel data from the CPU and transmits serial data after conversion. This device also receives serial data from the outside and transmits parallel data to the CPU after conversion

Control Word for 8251

There are two types of 16bit registers 1) MODE WORD REGISTER 2) COMMAND WORD REGISTER (Status)

The mode word defines general operating characteristics such as

i)Sync,Async Mode, Ii)Number of bits per character, Iii)Parity mode used Iv) If asynch then baud rate and no of stop bits V) Sync mode then sync characters and detection circuit

Mode Word Format

Asynchronous
D7 S2 D6 S1 D5 EP D4 PEN D3 L2 D2 L1 D1 B2 D0 B1

No of stop bits 00 = Invalid 01 = 1 bit 10 = 1.5 bits Enable Parity 11 = 2 bits Generation Chk 1=Even 0=Odd

Enable Parity 1=Enable 0=Disable Character Length 00=5bit 01=6bit 10=7bit 11=8bit Baud Rate Factor 00=Sync mode 01=1x 10=16x 11=64x

Mode Word Format

Synchronous
D7 SCS D6 ESD D5 EP D4 PEN D3 L2 D2 L1 D1 0 D0 0

Single Char Sync 0=Single 1=Double External Character Sync Detect 1-SYNDET is i/p 0-SYNDET is o/p

Enable Parity 1=Enable 0=Disable Character Length 00=5bit 01=6bit 10=7bit 11=8bit Baud Rate Factor 00=Sync mode 01=1x 10=16x 11=64x

Command Word
Used to enable transmitter and reciever
D7 EH D6 IR D5 RTS D4 ER D3 SBR K D2 RxE D1 DTR D0 TxEn

Status Word Format

Contains General Info about 8251
D7 D6 D5 D4 D3 D2 D1 D0

Problem
Configure 8251 in Asynchronous Transmitter mode with following specifications Select Baud Rate factor x 1 Character length 8 bits Odd parity Generation Number of stop bits = 1
Mode Word = 5D D7 0 D6 1 D5 0 D4 1 D3 1 D2 1 D1 0 D0 1

Control Word = 23 Transmit,Data Terminal,Ready and Request to Send ON D7 EH 0 D6 IR 0 D5 RTS 1 D4 ER 0 D3 SBRK 0 D2 RxE 0 D1 DTR 1 D0 TxEn 1

General Overview
Control Word 31 H Control Word 39 H

30H

8251 Transmitter

38H

8251 Reciever

USART
0000:1000 MOV AL, 4D 0000:1002 OUT 31, AL 0000:1004 OUT 39, AL 0000:1006 MOV AL, 11 0000:1008 OUT 31, AL 0000:100A MOV AL, 36 0000:100C OUT 39, AL 0000:100E MOV SI, 3000 0000:1011 MOV BX, 4000 0000:1014 MOV CL, 05 0000:1016 IN AL, 31 0000:1018 AND AL, 01 0000:101A JZ 1016 0000:101C MOV AL, [SI] 0000:101E OUT 30, AL 0000:101E OUT 30, AL 0000:1020 IN AL, 39 0000:1022 AND AL, 02 0000:1024 JZ 1020 0000:1026 IN AL, 38 0000:1028 MOV [BX], AL 0000:102A INC SI 0000:102B INC BX 0000:102C DEC CL 0000:102E JNZ 1016 0000:1030 INT 3 ;Mode word ;Set for both usarts

;Transmit enable for first

;Receive enable for second ;Source Transmitter Data ;Dest Reciever Data ;Counter blocks ;Check transmitter ready ;Mask all bits except last ;Keep waiting ;Get first block ;Send it to data port

Ports [Transmitter] Group A 8251 Mode Word : 31H Data to Send: 30H [Reciever] Group B 8251 Mode Word : 39H Data to Receive:38H

;Get reciever status ;Check the B1 bit for receive ready Wait ;Received data on port 38 ;Move it to contents of bx ;Increment SI ;Increment BX ;Decrement CL ;Go back to check transmitter ready instruction

8279
It is designed to interface and control keyboard and display peripherals.it relieves cpu from scanning keyboards and refreshing displays debouncing keys closures,blanking display etc. in 8279, keyboard display operation simulateously. operates in 3 modes Scanned keyboard mode Strobed input mode Scanned sensor matrix mode

Display section
display section display ram it is 16 * 8 bit display ram .the microprocessor can read or write the ram.the address location to be specified by command word display address register

Keyboard Interfacing

Registers

Ports
Port 31: Control Word Common Port 30: Data to be displayed
Left Entry Mode 2 Key Encoded Lockout 0 0 0 D D K K K

Right Entry Mode 2 Key Encoded Lockout 0 0 0 0 0 0 D 1 D 1 K 0 K 0 K 0

Both for 16x8

 Other registers Clock Prescalar

0 0 0 0 1 1 P 0 P 1 P 0 P 0 P 0

Write Display RAM

1 0 0 AI A

Divide frequency by this integer value 38

Mov al,08 ;command word for left entry mode Out 31,al Mov al,38 ;Program Clock set to 001PPPPP Out 31,al Mov al,90 ;Write Display RAM Out 31,al mov bx,1500 ;Pointer to data Mov cx,0010 ;Number of data 2012: mov al,[bx] ;data segment initialized Out 30,al Mov dx,ffff ; delay routine 2019: dec dx Jnz L4 Inc bx Loop 2012 Int 3