UNIT IV

STRUCTURAL MODELING
 TOPICS TO BE COVERED

• Parts Library
• Wiring of primitives
• Wiring of iterative networks
• Top-Down wiring
• Modeling Test Benches
 Parts Library
• library – holds all predefined cells

For any cell, the library holds

• Symbol
• Entity with ports and port clause
• Architecture
• Interface description
• Port types
 WIRING OF PRIMITIVES

• Models can be constructed by interconnecting

subcomponents
– A structural model lists the required subcomponents and
prescribes their interconnections

x
y carry
enable

result
• VHDL mechanisms to incorporate design
objects
– Using direct instantiation (not available prior to
VHDL-93)
– Using component declarations and instantiations
• Create idealized local components (i.e. declarations)
and connect them to local signals (i.e. instantiations)
• Component instantiations are then bound to VHDL
design objects either :
– Locally -- within the architecture declaring the component
– At higher levels of design hierarchy, via configurations
Structure Example
bit0
d_latch
d0 q0
d q
clk

bit1
d_latch
d1 q1
d q
clk

bit2
d_latch
d2 q2
d q
clk

bit3
d_latch
d3 q3
d q

gate clk
and2
en int_clk
a y
clk
b
 Structure Example
• First declare D-latch and and-gate entities
and architectures
entity d_latch is entity and2 is
port ( d, clk : in bit; q : out bit ); port ( a, b : in bit; y : out bit );
end entity d_latch; end entity and2;

architecture basic of d_latch is architecture basic of and2 is

begin begin
latch_behavior : process is and2_behavior : process is
begin begin
if clk = ‘1’ then y <= a and b after 2 ns;
q <= d after 2 ns; wait on a, b;
end if; end process and2_behavior;
wait on clk, d; end architecture basic;
end process latch_behavior;
end architecture basic;
 Structure Example
• Now use them to implement a register
architecture struct of reg4 is
signal int_clk : bit;
begin
bit0 : entity work.d_latch(basic)
port map ( d0, int_clk, q0 );
bit1 : entity work.d_latch(basic)
port map ( d1, int_clk, q1 );
bit2 : entity work.d_latch(basic)
port map ( d2, int_clk, q2 );
bit3 : entity work.d_latch(basic)
port map ( d3, int_clk, q3 );
gate : entity work.and2(basic)
port map ( en, clk, int_clk );
end architecture struct;
 WIRING OF ITERATIVE NETWORKS

• Can’t directly instantiate entity/architecture

pair
• Instead
– include component declarations in structural
architecture body
• templates for entity declarations
– instantiate components
– write a configuration declaration
• binds entity/architecture pair to each instantiated
component
 Structure Example – BOTTOM UP WIRING

• First declare D-latch and and-gate entities

and architectures
entity d_latch is entity and2 is
port ( d, clk : in bit; q : out bit ); port ( a, b : in bit; y : out bit );
end d_latch; end and2;

architecture basic of d_latch is architecture basic of and2 is

begin begin
latch_behavior : process and2_behavior : process
begin begin
if clk = ‘1’ then y <= a and b after 2 ns;
q <= d after 2 ns; wait on a, b;
end if; end process and2_behavior;
wait on clk, d; end basic;
end process latch_behavior;
end basic;
 Structure Example
• Declare corresponding components in
register architecture body
architecture struct of reg4 is
component d_latch
port ( d, clk : in bit; q : out bit );
end component;
component and2
port ( a, b : in bit; y : out bit );
end component;
signal int_clk : bit;
...
 Structure Example
• Now use them to implement the register
...
begin
bit0 : d_latch
port map ( d0, int_clk, q0 );
bit1 : d_latch
port map ( d1, int_clk, q1 );
bit2 : d_latch
port map ( d2, int_clk, q2 );
bit3 : d_latch
port map ( d3, int_clk, q3 );
gate : and2
port map ( en, clk, int_clk );
end struct;
 Structure Example
• Configure the register model
configuration basic_level of reg4 is
for struct
for all : d_latch
use entity work.d_latch(basic);
end for;
for all : and2
use entity work.and2(basic)
end for;
end for;
end basic_level;