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Bipolar 741 op-amp (mature, well-practiced, cheap) CMOS or BiCMOS op-amp designs (more recent, popular)
R. W. Knepper SC412, slide 8-1
We can shunt the common node bias resistor with a capacitor to reduce the negative impact on gain
Has no effect on gain reduction at low frequencies, however Large bypass capacitors are difficult to implement in IC design due to large area
The basic differential amplifier topology can be used for bipolar diff amp design or for CMOS diff amp design, or for other active devices, such as JFETs
Using these definitions, the inputs v1 and v2 can be written as linear combinations of the differential and common modes
v1 = vi,cm + vi,dm v2 = vi,cm vi,dm
Input signal is switching around ground Vref = 0 for this particular design
Both sides are DC-biased at ground on the base of Q1 and Q2
vBE is the forward base-emitter voltage across the junctions of the active devices Since Q1 and Q2 are assumed matched, Io splits evenly to both sides
IC1 = IC2 = Io/2
R. W. Knepper SC412, slide 8-5
Trench Isolation
Oxide lined, polysilicon filled
Highly doped extrinsic base lower Rb Emitter (arsenic) diffused from N+ poly SiGe Heterojunction BJT:
Typically 10-15% mole fraction of Ge graded into intrinsic base region (as shown), bandgap is narrowed in base, adding drift component to electron velocity
Since XB << Ln in the base, most of the injected electrons get to the collector without recombining with holes. Any holes that do recombine with electrons in the base are supplied as base current. Electrons reaching the collector are collected across the base-collector depletion region. Since most of the injected electrons reach the collector and only a few holes are injected into the emitter, or recombine with electrons in the base, IB << IC, implying that the device has a large current gain.
Shown at left are the effects of different NPN bias conditions on the energy bands and the electron concentrations: (a) No bias (thermal equilibrium)
Fermi levels are flat Electron concentration is ND in emitter and collector and ni2/NA in the base
(a)
(b)
Both junctions are forward-biased the same amount. No current flows even though the base is loaded with charge (electrons). Saturation condition: both junctions forward biased. Net electron flow from emitter to collector.
Saturation region:
Both E-B and C-B forward biased Base region is flooded with electrons
Cut-off region:
Both junction reverse biased No current flow
At higher (normal) VCE only the emitter-base junction is forward-biased, while the collectorbase junction is reverse-biased, resulting in the normal active (forward mode) region
The carrier concentration is pinned at zero (i.e. very small) at the collector junction, resulting in a linear (triangular) distribution of charge in the base Non-zero slope in normal active region is caused by base width narrowing due to increase in VCB reverse bias and corresponding increase in C-B depletion region (Early Effect named after Jim Early)
At even higher VCE the transistor enters the onset of avalanche breakdown at the CB junction The non-zero slope in the forward mode region is modeled, as shown below, with a linear term VCE/VA, where VA is the Early Voltage.
NPN DC Characteristics
Top left figure shows a set of collector characteristics (common emitter) for base current stepped from 0 to 30 uA for a SiGe HBT with emitter area of 0.5 x 2.5 um
Very flat curves indicate Early voltage greater than 70 volts.
Gummel plots showing log Ic and log Ib versus VBE indicate excellent SiGe NPN behavior and extremely low recombination current at low VBE
Beta remains constant at about 200 to VBE = 0.9 volt or higher
Harame, et al., IEEE Trans ED, Vol. 48, No. 11, Nov. 2001
IBM SiGe Design Kit Training: Technology, IBM Microelectronics, Burlington, VT, July 2002
The two curves in the plots are shifted by the area of the emitter.
Using minimum width for the emitter improves base resistance and therefore improves device performance.
Harame, et al., IEEE Trans ED, Vol. 48, No. 11, Nov. 2001
A small-signal model for the diff amp is shown below, where the Tx output collector resistance ro is assumed to be >> RC (in parallel) and is neglected We can derive the small-signal gain due to the differential input by applying KVL to loop A
va(t) (-va(t)) = 2va(t) = ib1rT1 ib2rT2 = 2ib1rT since ib1 = -ib2 and rT1= rT2 Or, ib1 = va(t)/rT and ib2 = - va(t)/rT
We can now find the gain with differential-mode input and single-ended output or with differential-mode input and differential output
Adm-se1 = v01/vidm = -gmRC/2 and Adm-se2 = + gmRC/2 Adm-diff = (v01 v02 )/ vidm = - gmRC
Since corresponding currents on the left and right side of the differential small-signal model are always equal and opposite, implying that no current ever flows throw rn
Node E acts as a virtual ground
If the output resistances of Q1 and Q2 are low enough to require keeping them in the analysis, we simply replace RC with the parallel combination of RC||ro for transistor Q1 and Q2
The common-mode currents from both inputs flow through rn as shown by the two loops
in = 2(Fo + 1) ib1 = 2 (Fo + 1) ib2 and therefore, vb = ibrT + 2(Fo+ 1)ibrn or ib = vb/[rT + 2(Fo+ 1)rn]
The common-mode gain with differential output is Acm-diff = (vo1 vo2)/vicm = 0 Do Example 8.1, p. 488
Using the definitions of differential mode and common mode inputs, respectively,
vidm = v1 v2 = 2vy sin [2t and vicm = (v1 + v2)/2 = vx cos [1t , we can obtain vo1 = Adm-se1 vidm + Acm-se1 vicm = - FoRC [(vy/ rT) sin [2t + (vx/{rT + 2 (Fo+ 1) rn}) cos [1t] The expression for v02 is similar except that the first term (differential mode) has a minus sign Note that the common mode output is reduced by the factor (Fo+ 1) in the denominator
For a bipolar diff amp with differential output, the CMRR is found to be
CMRR = |Adm-diff|/|Acm-diff| = |- gmRC| / 0 = infinity
In the case of the bipolar diff amp with single-ended output, CMRR is given by CMRR = |Adm-se|/|Acm-se| = | gmRC| / | FoRC/[rT + 2(Fo+ 1)rn]| = [rT + 2(Fo+ 1)rn]/2rT = ~ Forn/rT = gmrn = ICrn/LVT = Iorn/2LVT since Fo = gmrT and VT is defined as kT/q CMRR is often expressed in decibels, in which case the definition becomes
CMRR = 20 log (|Adm|/|Acm|)
By using the Ebers-Moll dc model for the NPN transistors, we can determine the voltage at node E IE = IEO [exp (qVBE/LkT) 1] = IEO exp (qVBE/LkT)
= Io/2 or, VBE = (LkT/q) ln (IE/IEO) Typically, VBE = 0.75-0.85 V in modern NPN transistors
It is important to design RC such that vout never drops so low so as to force Q1 or Q2 into saturation.
Design Conditions
Differential-mode, single-ended gain > = 50 Common-mode, single-ended gain < = 0.2
Completed design is shown above In class Exercise: 8.4, 8.5, & 8.6
R. W. Knepper SC412, slide 8-26
An alternate method of generating Io is to use an NPN transistor current source similar to that shown at the left
Q3 is an NPN biased in the forward active region so that rn (given by the inverse slope of the collector characteristics) is very high RA and RB form a voltage divider establishing VB = VEE x RA/(RA + RB) where VEE is <0 The voltage across RE can be used to find Io VRE = VB Vf VEE Io = (VB Vf VEE)/RE is the bias current provided to the diff amp
Obtain vT3 by applying KVL to the 3 left-most resistors to obtain ib3 and multiply by rT3 vT3 = -itest RE rT3 /[RE + rT3 + RP] If we multiply this result by gm3 and substract from itest, we obtain io3 which can be used to find vo3 by multiplying by r03 vo3 = itest{1 + gm3RE rT3 /[RE + rT3 + RP]}ro3 ve can be found as (itest + ib3) x RE ve = itest (rT3 + RP) RE/(RE + rT3 + RP) Adding vo3+ ve = vtest, we obtain rn = vtest/itest rn = RE || (rT3 + RP) + r03 [1 + FoRE/(RE+ rT3+RP)] Do Exercise 8.8 and 8.9 in class.
R. W. Knepper SC412, slide 8-28
Variations on the basic current mirror circuit can be used to generate 2X or 3X or maybe 10X the original reference current by using several bias NPN transistors in parallel
Or alternately, by using an emitter that has 2X or 3X or 10X emitter stripes and is otherwise identical to the reference transistor
Advantages
One reference current generator can be used to provide bias to several stages Very high incremental output impedance can be obtained from the current mirror The technique can be used in both bipolar and in CMOS/BiCMOS technologies
R. W. Knepper SC412, slide 8-29
We can find IA by dividing the voltage drop across RA by the resistance value
IA = (VCC VBE1 VEE) / RA Assuming that the two base currents are small, we can say IA = Iref Because of the current mirror action, the VBE1 set up in Q1 to sustain current Iref will be equal to VBE2, the base-emitter voltage in Q2 Therefore, Io = Iref = IA Note: corrections for IB1 and IB2 can easily be made is needed Note 2: Q2 must be maintained in its forward active region
R. W. Knepper SC412, slide 8-30
Design Procedure:
Set Io = IA = 3 mA RA = (0 VBE = VEE)/3mA = 3.1K
where we used VBE = 0.7 volt
RC1 & RC2 can be found as follows: RC1 = RC2 = 5V/1.5 mA = 3.3K
Check VCE of Q2, Q3, and Q4 to see if they are in normal active region
VC = VCC 1.5 mA x 3.3K = 5V VE = 0 VBE = -0.7V VCE = 5 (-0.7) = 5.7V for Q2 and Q3 For Q2 VCE = -0.7V (-10) = -9.3V
Check the VCE of each device to check for normal active region and calculate power in circuit.
The total circuit power is found by computing the sum of the three current source currents multiplied by the source-sink voltage differential for each.
Q1: 0.93mA x 10V = 9.3mW Q2: 0.93mA x 20V = 18.6mW Q3/Q4: 1.86mA x 20V = 37.2 mW
Total circuit power = 65.1 mW
Design procedure:
As in the standard current mirror, we can find Iref as follows: Iref = (VCC VEE VBE1)/RA But, in contrast to the standard current mirror, VBE2 will not be equal to VBE1 VBE1 = VBE2 + IE2R2 Using the Ebers-Moll model for emitter current IE = IEO (exp[VBE/LVT] 1) = ~ IEO exp[VBE/LVT] We can invert this expression and insert it into the above equation for VBE1 to obtain IE2 = (LVT/R2) ln(IE1/IE2) = Io = (LVT/R2) ln(Iref/Io) Since this is not a closed form solution, an iterative approach can be used to solve for Io by starting with a best guess.
R. W. Knepper SC412, slide 8-33
Example iteration procedure: Assume that Iref = 1 mA and R2 = 500 ohms. Guess Io inside ln term. Find LHS Io. 1. Initial guess = 0.5 mA, then Io = 0.036mA 2. Try a guess of 0.2 mA, then Io = 0.083mA 3. Try a guess of 0.1mA, then Io = 0.119mA 4. Try a guess of 0.11mA, then Io = 0.114mA Close enough!!
However, with a number of approximations and using the relation IoR2/LVT= ln (Iref/Io), the expression may usually be simplified to
rn = r02 [1 + ln (Iref/Io)]
Current Io is presumed to split equally on the left and right legs of the diff amp The voltage rails are now called VDD and VSS Before going into the biasing and small signal models, we will take a look at MOSFET devices and models
The voltage Vds = Vgs Vt = Vdssat is the pinch-off voltage where the channel pinches off at the drain junction.
Further increase in Vds simply increases the voltage between the drain and the channel pinchoff point, and does not increase the voltage V(y) along the channel.
Therefore, IDS remains constant for further increases in Vds and we say the device is in the saturation region (or active region) with
IDS = Qn Cox (W/L) (Vgs Vt)2
The transconductance in saturation can be found by differentiating the expression for IDS with Vgs, giving gm = QnCox (W/L) (Vgs Vt) = [2 QnCox (W/L) IDS]
From this new expression one can derive an expression for the output drain-source resistance of the NMOS transistor in the saturation region as
rds = 1/(dIDS/dVDS) = 1/(PIDS) where P is defined below and kds = [2ISIIo/qNA]
The gate-to-channel capacitance is evenly divided between source and drain in the linear (triode) region, but is effectively connected only to the source at pinchoff
Integration of the channel charge shows that only 2/3 of Cgc becomes part of Cgs in the saturation (active) region A similar reasoning is used to partition Ccx (CCB in picture) between Csx and Cdx
Cgx (gate-to-substrate) is zero when Vgs > Vt, but increases to CoxW(L - 2(L) in the accumulation region.
Setting the magnitude of the current gain to unity, we obtain fT = gm/2T(Cgs + Cgd)
Because of the manner in which it is derived, fT neglects series gate resistance rg and capacitance on the output, such as Cgd. Unity power gain bandwidth product fmax (frequency where power gain falls to 1): A useful expression for the unity power gain point fmax is given by
fmax = [fT / 8TrgCgd]
These figure of merits are useful for technology comparisons and are also often used in high frequency amplifier design
Note that fT increases with small L (inverse with L2) and with increasing Vgs This is a result based only on a long-channel assumption.
As the channel shortens, the electric field increases beyond the point where mobility is constant any longer (typical of todays advanced CMOS technology)
Scattering of electrons by optical phonons causes the drift velocity to saturate at about 1E7 cm/sec, occurring at an electric field Esat = ~ 1E4 V/cm.
Beyond this point further increases in E field result in diminishing increases in carrier velocity
This effect represents itself in the IDS current equation by a reduction in Vdssat below Vgs Vt thus reducing IDSsat to less than nCox(W/L)(Vgs Vt)2 If we redefine Vdsat to be determined by the minimum of (Vgs Vt) and LEsat (i.e. sort of having (Vgs Vt) and LEsat in parallel), we can write Vdsat = [(Vgs Vt)(LEsat)] / [(Vgs Vt) + (LEsat)] We can then rewrite the current equation as IDS = nCox(W/L)(Vgs Vt)(Vdsat) = WCox(Vgs Vt) vsat [1 + LEsat/(Vgs Vt)]1
where vsat is the saturation velocity given by nEsat and n is the low field mobility
PHI=0.7, TOX=9.5E-9, XJ=0.2U TPG=1 (-1), VTO=0.7 (-0.95) DELTA=0.88(0.25), LD=5E-8 (7E-8) KP=1.56E-4 (4.8E-5), UO=420 (130) THETA=0.23 (0.20), RSH=2.0 (2.5) GAMMA=0.62 (0.52) NSUB=1.4E17 (1.0E17) NFS=7.2E11 (6.5E11) VMAX=1.8E5 (3E5) ETA=0.02125 (0.025) KAPPA=0.1 (8) CGDO=CGSO=3.0E-10 (3.5E-10) CGBO=4.5E-10, CJ=5.5E-4 (9.5E-4) MJ=0.6 (0.5), CJSW=3E-10 (2E-10) MJSW=0.35 (0.25), PB=1.1 (1.0)
R. W. Knepper SC412, slide 8-43
MOSFET with Vgs > VT causes formation of a channel (inversion layer) connecting source to drain
With Vds > 0, a positive current Ids flows from drain to source (N-FET) Depletion layer exists from source, drain, & channel N region to P substrate
VTN = - Qfc/Cox + {2qINA(2JF + Vsx)}/Cox + JMS + 2JF for N-FETs VTP = - Qfc/Cox - {2qINA(|2JF + Vsw|)}/Cox + JMS + |2JF| for P-FETs
R. W. Knepper SC412, page 8-44
oxide gate
P+ P+
source
P substrate
drain
source
N well
drain
N channel device
P channel device
VTN = - Qfc/Cox + {2qINA(2JF + Vsx)}/Cox + JMS + 2JF for N-FETs VTP = - Qfc/Cox - {2qINA(|2JF + Vsw|)}/Cox + JMS + |2JF| for P-FETs
Threshold Voltage is a square root function of sourceto-substrate per chart at left. Applies to both N and P devices using |Vsx+2JF| Implications for circuit applications where the source voltage rises significantly above ground potential.
Assuming that the W of Q6 and Q7 are identical to that of Qref, then we can see that the above current equation will require that VGS6 = VGS7 = VGSref = 1/3 (VDD VSS), where we have neglected any dependence of VT on Vsx. If we set the current in Q3 to that in Qref, we can obtain the following expression VDS3 = E(VDD VSS)/3 + [1 - E]VT where E = (Kref/2Kpu) Thus, setting Kref = 2Kpu leads to VDS3 = 1/3 (VDD VSS) or Vout1 = VDD VDS3 = 2/3 VDD + 1/3 VSS
The current mirror current source is modeled simply by its output impedance (in saturation) Each transistor is presumed to be in its saturation (constant current) region
With the above approximation for the load device, we can simplify the NMOS diff amp incremental model to that shown on the following slide
R. W. Knepper SC412, slide 8-49
Common mode gain can also be found from the small signal circuit below
Acm-se1 = Acm-se2 = -gm1rth3/[1 + 2ro5gm1(1 + '1)] = ~ rth3/2ro5(1 + '1)
The gain of the right hand (inverting) leg will be higher than the gain of the left side Since all transistors have grounded source operation, there is no body effect to worry about with this CMOS diff amp circuit