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Introduction to
Analog-Digital-Converter
Analog-Digital-Converter
Dr.-Ing. Frank Sill
Department of Electrical Engineering, Federal University of Minas Gerais,
Av. Antnio Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil
franksill@ufmg.br
http://www.cpdee.ufmg.br/~frank/
Analog Digital Converter 2 Copyright Sill, 2008
Agenda
Agenda
Introduction
Nyquist-Rate ADCs
Oversampling ADC
Practical Issues
ADC = Analog-Digital-Converter
What is aliasing?
Analog Digital Converter 6 Copyright Sill, 2008
ADC Values
ADC Values
8 Bit = 2
8
= 256 quantization level,
10 Bit = 2
10
= 1024 quantization level
Reference voltage V
ref
: Analog input signal V
in
is related
to digital output signal D
out
through V
ref
with:
V
in
= V
ref
(D
0
2
-1
+ D
1
2
-2
+ + D
N-1
2
-N
)
Example: N = 3 Bit, V
ref
= 1V, D
out
= 011
=> V
in
= 1V ( 2
-2
+ 2
-3
) = 1V (0.25 + 0.125) = 0.375V
ADC
V
in
D
out
= D
0
D
1
D
N-1
V
ref
Analog Digital Converter 7 Copyright Sill, 2008
ADC Values contd
ADC Values contd
V
LSB
: Minimum measurable voltage difference in
ideal case (LSB least significant Bit)
V
LSB
= V
ref
/ 2
N
V
in
= V
LSB
(D
0
2
N-1
+ D
1
2
N-2
+ + D
N-1
2
0
)
Example: N = 3 Bit, V
ref
= 1V, D
out
= 011
=> V
LSB
= 1V / 2
3
= 0.125V
=> V
in
= 0.125V ( 2
1
+ 2
0
) = 0.125V 3 = 0.375V
Ideal: all V = V
LSB
V
FSR
: Difference between highest and lowest
measurable voltages (FSR full scale range)
Analog Digital Converter 8 Copyright Sill, 2008
ADC Values contd
ADC Values contd
SINAD
ENOB
, 10log
signal signal
db
noise noise
P P
SNR SNR
P P
_
,
Analog Digital Converter 9 Copyright Sill, 2008
Ideal ADC
Ideal ADC
000
001
010
011
100
101
110
111
8
ref
V
D
i
g
i
t
a
l
O
u
t
p
u
t
D
o
u
t
Analog Input V
in
7
8
ref
V
4
8
ref
V
V, V
LSB
V
FSR
Analog Digital Converter 10 Copyright Sill, 2008
Further ADC Values
Further ADC Values
Power dissipation
Sampling rate (f
samp
): Rate at which new digital values
are sampled from the analog signal (also: sample
000
001
010
011
100
101
110
111
in
V
2
LSB
V
2
LSB
V
7
8
ref
V
D
o
u
t
2 2
LSB LSB
V V
<
Analog Digital Converter 12 Copyright Sill, 2008
Quantization Error (3-Bit Flash)
Quantization Error (3-Bit Flash)
Eugenio Di Gioia, Sigma-Delta-A/D-Wandler, 2007
sample
sample
A
m
p
l
i
t
u
d
e
E
r
r
o
r
Analog Digital Converter 13 Copyright Sill, 2008
Offset Error
Offset Error
Deviation of V from V
LSB
value (in V
LSB
)
Nyquist criterion:
f
samp
more than two times higher than highest frequency
component f
in
of input signal: f
samp
> 2f
in
Input signal
(with f
in
)
Reconstructed
output signal
Measured data points
(sample rate: f
samp
)
Analog Digital Converter 20 Copyright Sill, 2008
3. Nyquist-Rate ADCs
3. Nyquist-Rate ADCs
Sampling frequency f
samp
is in the same range as
frequency f
in
of input signal
Integrating
Successive Approximation
Algorithmic
Flash
Two-Level Flash
Pipelined
Analog Digital Converter 22 Copyright Sill, 2008
Integrating (Dual Slope) ADCs
Integrating (Dual Slope) ADCs
Q
load
= V
in
/ R1 T
load
Q
ref
= -V
ref
/ R1 T = -Q
load
=> V
in
= V
ref
T / T
load
Compare V
D/A
with input signal V
in
Modify V
D/A
by D
0
D
1
D
2
D
N-1
until closest possible value
to V
in
is reached
S&H
Logic
DAC
D
0
D
1
D
N-1
V
in
V
ref
V
D/A
Analog Digital Converter 26 Copyright Sill, 2008
Successive Approximation ADC contd
Successive Approximation ADC contd
S&H
Logic
DAC
D
0
D
1
D
N-1
V
in
V
ref
V
D/A
Comparsion of V
D/A
with
2
V
ref
2
in
V
ref
V >
2
in
V
ref
V <
Comp. w.
4
V
ref
Comp. w.
3
4
V
ref
4
in
V
ref
V >
4
in
V
ref
V <
4
in
V
ref
V >
4
in
V
ref
V <
Analog Digital Converter 27 Copyright Sill, 2008
Successive Approximation ADC contd
Successive Approximation ADC contd
P. Fischer, VLSI-Design - ADC und DAC, Uni Mannheim, 2005
Iterations
in
V
8
ref
V
4
8
ref
V
7
8
ref
V
1. 2. final
result
V
D/A
100
110
010
111
101
011
001
111
110
101
100
011
010
001
000
3.
Analog Digital Converter 28 Copyright Sill, 2008
Successive Approx.: pros and cons
Successive Approx.: pros and cons
Low Area / Low Power
High effort for DAC
Early wrong decision leads to false result
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Algorithmic ADC
Algorithmic ADC
Instead of modifying V
ref
doubling of error
voltage (V
ref
stays constant)
V
in S&H
S&H
X2
S1
V
ref
/4
-V
ref
/4
S2
D
0
D
1
D
N-1
Shift register
Analog Digital Converter 30 Copyright Sill, 2008
Algorithmic ADC cont
Algorithmic ADC cont
Start
Sample V = V
in
, i = 1
D
i
= 1
V > 0
D
i
= 0
V = 2(V - V
ref
/4) V = 2(V + V
ref
/4)
i = i+1
i > N
Stop
yes
no
yes
V
in
S&H
X2
S1
V
ref
/4
-V
ref
/4
S2
D
0
D
1
D
N-1
Shift register
no
S&H
D.A.. Johns, K. Martin, Analog Integrated Circuit design, John Wiley & Sons, 1997
Analog Digital Converter 31 Copyright Sill, 2008
Algorithmic ADC: pros and cons
Algorithmic ADC: pros and cons
Less analog circuitry than Succ. Approx.
ADC
Low Power / Low Area
High effort for multiply-by-two gain amp
Analog Digital Converter 32 Copyright Sill, 2008
Flash ADC
Flash ADC
V
in
V
ref
Over range
D
0
D
1
D
N-1
(2
N
-1) to N
encoder
R/2
R
R/2
R
R
R
R
R
R
V
in
connected with 2
N
comparators in parallel
Comparators connected
to resistor string
Thermometer code
R/2-resistors on bottom
and top for 0.5 LSB
offset
Analog Digital Converter 33 Copyright Sill, 2008
Some Flash ADC design issues
Some Flash ADC design issues
7
8
ref
V
D
o
u
t
2 2
LSB LSB
V V
<
Analog Digital Converter 42 Copyright Sill, 2008
Quantization Noise
Quantization Noise
LSB
LSB
V
V
LSB
p d
p
V
p()
2
LSB
V
2
LSB
V
p
Analog Digital Converter 43 Copyright Sill, 2008
Quantization Noise contd
Quantization Noise contd
F.e. V
in
is sinusoidal wave SNR = (6.02 N + 1.76) dB
( )
1/ 2
1/ 2
/ 2
2 2
_
/ 2
1
12
LSB
LSB
V
LSB
qn RMS
LSB
V
V
V p d d
V
+
1
1
1
1
1 ]
]
Analog Digital Converter 44 Copyright Sill, 2008
Quantization Noise contd
Quantization Noise contd
Spectral density S
(f)
2
s
f
2
s
f
f
1
12
LSB
s
V
S
f
( )
/ 2
2
2
/ 2
12
s
s
f
LSB
f
V
P S f df
+
2
s
f
2
s
f
f
H(f)
|H(f)|
0
2
f
0
2
f
1
V
in
(f)
0
2
s
f
OSR
f
results to:
Doubling of f
s
increases SNR by 3 dB
F.e. V
in
is sinusoidal wave
( ) ( )
2 2 2 2
_
5 1 7 0 5 1 7 0
24
RMS Oversampling
V
+ + +
H(z)
Integrator Quantizer
DAC
X Y
E
( )
1
1
1 1
H
Y X E X H
H H
+ >>
+ +
Analog Digital Converter 51 Copyright Sill, 2008
Noise Shaping contd
Noise Shaping contd
up to f
in
= 100 kHz (and more)
1-Bit DAC
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OS and NS in Frequency Domain
OS and NS in Frequency Domain
P
o
w
e
r
f
s
/2 = OSRf
0
/2
f
0
/2 f
Digital filter response
Oversampling
P
o
w
e
r
f
s
/2 f
0
/2 f
Oversampling and noise shaping
P
o
w
e
r
f
0
/2 f
Signal
amplitude
Average
quantization noise
Analog Digital Converter 53 Copyright Sill, 2008
DAC
Comparator
V
ref
= 2.5 V
V
in
= 1.2 V
( ) ( )
in
v t t dt
( ) ( )
in
v t t
Sigma Delta ADC Example
Sigma Delta ADC Example
1.2
-1.3
3.7
-1.3
1.2
-0.1
3.6
2.3
1
0
1
1
2.5
-2.5
2.5
2.5
Analog Digital Converter 54 Copyright Sill, 2008
Sigma Delta ADC Example (Curves)
Sigma Delta ADC Example (Curves)
http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma_D.html
H(z)
I
n
t
e
g
r
a
t
o
r
1
B
i
t
-
Q
u
a
n
t
i
z
e
r
CLK
D
A
C
Analog Digital Converter 55 Copyright Sill, 2008
Sigma Delta ADC: pros and cons
Sigma Delta ADC: pros and cons
High resolution
Less effort for analog circuitry
Low speed
High CLK-frequency
Currently popular for audio applications
Analog Digital Converter 56 Copyright Sill, 2008
5. Practical issues
5. Practical issues
Noise
Wire delays
Analog Digital Converter 58 Copyright Sill, 2008
Parasitic Component Example
Parasitic Component Example
Example 1: V
ref
= 5V, 10 Bit resolution
V
LSB
= 5V / 2
10
= 5V / 1024 = 4.9 mV
Every noise must be lower than 4.9 mV
Example 2: V
ref
= 5V, 16 Bit resolution
V
LSB
= 5V / 2
16
= 5V / 65536 = 76 V
Every noise must be lower than 76 V
Analog Digital Converter 60 Copyright Sill, 2008
PCB- versus IC-Design
PCB- versus IC-Design
Demands:
Reduction of V
DD
:
Possible solutions:
Dynamic change of V
DD
depending on required
performance
Reduction of f
clk
:
Dynamic change of f
clk
Analog Digital Converter 66 Copyright Sill, 2008
Low Power ADC Design contd
Low Power ADC Design contd
Reduction of C
load
:
C
load
depends on transistor count and transistor size,
wire count and wire length
Possible Solutions:
Reduction of :
Possible Solutions:
Asynchronous designs
Analog Digital Converter 68 Copyright Sill, 2008
Which ADC for Low Power?
Which ADC for Low Power?
Less components
Problem: Counter
Peak power:
Which resolution?
Which speed?
v(t)
time
2
0
_
[ ]
n
i
RMS discrete
x n
V
n
x[n]
n
RMS: root mean square
Analog Digital Converter 77 Copyright Sill, 2008
Voltage supply reduction
Voltage supply reduction
[Tan00]
[Tan00]
Threshold of MOS
transistors.
Limits of conduction in
analog switches.