Introduction to Testbenches

Objectives
After completing this module, you will be able to:

Define a testbench Describe behavioral modeling Write a simple testbench

Introduction to Testbenches - 6 - 3

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Outline

Testbench Concept Behavioral Coding Assertions Testbench Examples Summary

Introduction to Testbenches - 6 - 4

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Testbench Concept

A VHDL testbench is a virtual test bed

An upper-level hierarchical VHDL structure that applies input stimulus to a Unit Under Test (UUT) and monitors the output to verify functionality

CNTR32_TB
entity

CNTR32
entity

D_IN RST LOAD CLK

Q_OUT

TC

Introduction to Testbenches - 6 - 5

2007 Xilinx, Inc. All Rights Reserved

Application of a Testbench
Fewer details, verify design concept

Behavioral

RTL
AND_OR2 DFF

Logic
Technologyspecific details, slower design entry and simulation
Introduction to Testbenches - 6 - 6

Layout
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CLB_ R5C5

CLB_ R5C6

Complete IEEE 1076

IEEE 1076 (Synthesis)

IEEE 1076 (Modeling)

Behavioral modeling in VHDL utilizes the broad capabilities of the language

Introduction to Testbenches - 6 - 7
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Simulation I/O Flexibility

VHDL provides considerable flexibility for declaring and accessing files, along with various formats of data inputs and outputs

TESTBENCH entity UUT

entity

Text-based data operations are specified in the textio package

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Introduction to Testbenches - 6 - 8

Maintaining Consistency

Ideally, the same testbench could be applied at each stage of verification

VHDL modules

1. Behavioral/RTL simulation: Execute RTL source code 2. Post-synthesis VHDL simulation: Execute structural VHD file 3. VHDL timing simulation: Execute post-layout structural VHD and SDF file

VITAL

Synthesis

Place & Route

SDF and Structural VHD

Introduction to Testbenches - 6 - 9

2007 Xilinx, Inc. All Rights Reserved

Outline

Testbench Concept Behavioral Coding Assertions Testbench Examples Summary

Introduction to Testbenches - 6 - 10

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Behavioral Coding

A testbench (behavioral) description has advantages not available in RTL-level code or actual hardware

Values stored in signal Model bus input and output

signal RST: std_logic := 0 ; D_IN <= XFFFF0000 ;

No need to consider propagation delay Model timing as necessary Arbitrary sequencing of events
Z <= A and B after 2 ns ; RST <= 1 after 25 ns, 0 after 50 ns ;

Introduction to Testbenches - 6 - 11

2007 Xilinx, Inc. All Rights Reserved

Verify at Each Level

A VHDL design is typically built from the bottom up; a unique testbench should be used to verify the logic at each hierarchical stage

TOP_LVL_TB MID_LVL_TB LEAF_LVL_TB

Introduction to Testbenches - 6 - 12

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Outline

Testbench Concept Behavioral Coding Assertions Testbench Examples Summary

Introduction to Testbenches - 6 - 13

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VHDL Assertion Statements

Assertion statements can be used to test conditions during simulation without creating additional logic

They can also be used to halt simulation

TEST_FULL_ADD : process begin for i in DATA_FRAMErange loop SUM_EXPECTED <= DATA_FRAME.EXP; SUM_OUT <= ALU_OUT ; ... wait for 100 ns; assert SUM_EXPECTED = SUM_OUT report "ERROR: output SUM is incorrect" severity warning ; end loop; wait; end process ; end architecture TEST ;

Introduction to Testbenches - 6 - 14

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Assertion Syntax
VHDL sequential statement Suitable for behavioral/RTL code User-defined Boolean expression If true, nothing happens

Can test any Boolean expression

If false, use report and/or severity level

Optional User-defined text string, including concatenations Should be concise and informative

assert

SUM_EXPECTED = SUM_OUT

report
severity

"ERROR: output SUM is incorrect"

warning ;

User-defined text string, including concatenations

Can also use predefined text (for example, constants of type string)

Optional (if present, placed after report)

type severity_level is (note, warning, error, failure ); Can be used to halt simulation

Communicate to simulator
User sets threshold to halt simulation Note that semicolon appears here

Introduction to Testbenches - 6 - 15

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Outline

Testbench Concept Behavioral Coding Assertions Testbench Examples Summary

Introduction to Testbenches - 6 - 16

2007 Xilinx, Inc. All Rights Reserved

Components of a Testbench

Entity, which defines a testbench top-level structure

A testbench usually does not have ports

Internal signals, which will drive the stimuli into the UUT and monitor the response from the UUT

Signal to drive and monitor

UUT instantiation Stimuli generation

Write statements to create stimulus Process Self-testing statements that will report values, error, and warnings Text I/O routines in VHDL
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Response monitoring and comparing

Introduction to Testbenches - 6 - 17

Introduction to VHDL Processes

A process is a group of statements that are executed sequentially

All processes are concurrent to each other

constant PERIOD : time := 10 ns ;
...

Label (Optional)

STIM1: process begin CLK <= not CLK ; wait for PERIOD / 2 ;

Wait Condition

Sequential Statements;

end process STIM1 ;

End; Loops Back to Top

constant PERIOD : time := 10 ns ;

...

Indefinite Suspension

STIM2: process begin wait for 500 ns; LOAD <= 1 ; wait for PERIOD ; LOAD <= 0 ; wait ; end process STIM2 ;
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Sequential Statements;

Introduction to Testbenches - 6 - 18

VHDL Processes in RTL Coding

A process is a group of statements that are executed sequentially

Processes appear in all areas of VHDL coding, from behavioral to RTL

A B SEL
Label (Optional)

entity MUX21 is port ( A, B, SEL: in std_logic ; OUT1 : out std_logic ); end entity MUX21 ; architecture RTL of MUX21 is begin

End; Loops Back to Top

MUX2: process ( A, B, SEL ) begin case SEL is when 0 => OUT1 <= A ; when 1 => OUT1 <= B ; when others => OUT1 <= X ; end case ; end process MUX2 ;
end architecture RTL ;

Sensitivity List; (Implied Wait)

Sequential Statements;

Introduction to Testbenches - 6 - 19

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CNTR32 Testbench

A simple testbench for the entity CNTR32 might be constructed as follows

CNTR32_TB D_BUS CNTR_32 Q_BUS

entity CNTR32_TB is end entity CNTR32_TB ;

architecture TEST of CNTR32_TB is

LOAD component CNTR32 port ( D_IN : in std_logic_vector (31 downto 0 ); CLK, RST, LOAD : in std_logic ; Q_OUT : out std_logic_vector (31 downto 0 ) ; end component ; signal D_BUS, Q_BUS : std_logic_vector (31 downto 0 ); signal CLOCK, RESET, LOAD : std_logic ; begin UUT : CNTR32 port map ( D_BUS, CLOCK, RESET, LOAD, Q_BUS ); ( continued )

CLOCK

RESET

Lab
Marker

Introduction to Testbenches - 6 - 20

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Stimulus

The most important component of the testbench is the process that actually provides the stimulus

(continued)

STIMULUS : process
begin RESET <= 1; wait for 100 ns; RESET <= 0; D_BUS <= XFFFF0000 ; CLOCK <= 1;
wait for 25 ns; D_BUS <= X00000001 ; CLOCK <= 0; LOAD <= 1 : wait for 25 ns; CLOCK <= 1; wait ; end process STIMULUS ; end architecture TEST ;

In simulation, default initialization for type std_logic is U and 0 for type bit

Lab
Marker

Introduction to Testbenches - 6 - 21

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Creating Clock Signals

To create a free-running clock for a testbench

1. Declare the clock signal and initialize it to either 1 or 0

signal CLK_SIG: std_logic := 1 ;

2. Create a concurrent assignment that inverts the clock signal at the appropriate interval for the intended frequency

CLK_SIG <= not CLK_SIG after 5 ns ;

If the clock will be other than a 50/50 duty cycle, use separate invert and wait statements within a process

Introduction to Testbenches - 6 - 22

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Other Clock Approaches

The example on the left shows a non-50/50 duty-cycle clock; the example on the right includes the clock signal initialization
architecture TEST of CNTR32 is signal CLK_SIG : std_logic ; constant PERIOD : time := 10 ns ; begin architecture TEST of CNTR32 is signal CLK_SIG : std_logic ; constant PERIOD : time := 10 ns ; begin

CLK_STIM: process begin CLK_SIG <= 1 ; wait for PERIOD * 0.4 ; CLK_SIG <= 0 ; wait for PERIOD * 0.6 ; end process CLK_STIM ;

CLK_STIM2: process begin if CLK_SIG = 'U' then CLK_SIG <= '1' ; wait for PERIOD /2 ; end if; CLK_SIG <= not CLK_SIG ; wait for PERIOD /2 ; end process CLK_STIM2 ;
2007 Xilinx, Inc. All Rights Reserved

Introduction to Testbenches - 6 - 23

Initializing Signals

Any signal can be initialized by using a concurrent assignment or process

RST_SIG <= 1, 0 after 50 ns, 1 after 125 ns ;
INIT: process begin RST_SIG <= 1; wait for 50 ns ; RST_SIG <= 0 ; wait for 75 ns ; RST_SIG <= 1 ; wait ; end process INIT ; Lab
Marker
Introduction to Testbenches - 6 - 24
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Concurrent Statement; Time is Absolute

Sequential Statement; Time is Relative

In both cases, the signal RST_sig is initialized to 1 at time zero, then 0 at time 50 ns; 75 ns later, it is deasserted for the duration of the simulation

Outline

Testbench Concept Behavioral Coding Assertions Testbench Examples Summary

Introduction to Testbenches - 6 - 25

2007 Xilinx, Inc. All Rights Reserved

Knowledge Check

List the basic elements of a typical testbench

Can an RTL model be simulated in a behavioral environment?

Which of the following declarations would not be part of a testbench? [ ] Signal(s) [ ] Component(s) [ ] Port(s) [ ] Architecture
How can a stimulus process be made to repeat throughout simulation?

Introduction to Testbenches - 6 - 27

2007 Xilinx, Inc. All Rights Reserved

Answers

List the basic elements of a typical testbench

Top-level entity, UUT, signals for inputs and outputs, and input stimulus Yes

Can an RTL model be simulated in a behavioral environment?

Which of the following declarations would not be part of a testbench? [ ] Signal(s) [ ] Component(s) [X ] Port(s) [ ] Architecture How can a stimulus process be made to repeat throughout simulation?

By not using the unconditional wait command within the process block

Introduction to Testbenches - 6 - 28

2007 Xilinx, Inc. All Rights Reserved

Summary

A VHDL testbench is used to verify functionality Testbenches cannot be synthesized Testbenches utilize the full range of the VHDL language VHDL models hardware by using concurrent operations The same testbench can be applied at each stage of verification

Introduction to Testbenches - 6 - 29

2007 Xilinx, Inc. All Rights Reserved