Shabnam shahreen sifat Course: CSC311

Instructor: Mr. Mohammad Noor Nabi

Introduction
A common technique for improving performance in computer
systems (both hardware and software) is to utilize caching for frequently accessed information. This lowers the average cost of accessing the information, providing greater performance for the overall system. In the Intel Pentium 4 Processor

architecture, caching is a critical component of the system's

performance.

Caching in Pentium 4 Processor

The Pentium 4 has three levels of cache:
Level 1 cache Level 2 cache Level 3 cache

Level 1 Cache
The level 1 cache is a split cache. 8KB in size.

four-way set associative. This means that each set is

made up of four lines in cache.

The replacement algorithm used for this is a least

recently used algorithm.

The line size is 64 bytes.

Level 1 Cache
The level 1 cache is small to reduce latency, taking 2

cycles for an integer data cache hit and 6 cycles for a

floating point.
Instead of a classic level 1 instruction cache, the Pentium 4

uses a trace cache which takes advantage of the advanced

branch prediction algorithms.

Trace Cache
After the instructions have been decoded into micro-ops,

they are stored in the trace cache.

Six micro-ops are stored for each trace line. The trace

cache can store up to 12K micro-ops.

Since the instructions have already been decoded, the

hardware knows about any branches and fetches instructions that follow the branch.

Trace Cache
Problems might occur in the case of conditional branches if

the wrong one is predicted and a lot of additional instructions that are not needed have been pre-fetched and

decoded into the cache.

We would also have to wait for the cache to fetch the

correct instruction from the level 2 cache if the correct

branch was not stored in the cache. This may take up to 7 cycles, more if the branch is not found in the level 2 cache.

Advantage of Trace Cache

If the predictions work well, the cache is able to

provide three micro-ops per cycle to the execution

scheduler.
This also means that since the trace cache is only

storing instructions that will actually get executed, it is making more efficient use of the limited space.

Level 2 Cache
The level 2 cache is a unified cache.
256KB in size. eight-way set associative. This means that each

set is made up of eight lines in cache.

The line size is 128 bytes The replacement algorithm used for this is a

least recently used algorithm.

Level 2 Cache
The increase in size and set size means that it will reduce

the chances of a miss occurring when accessing this cache,

increasing its effectiveness.

The increase in line size can cause higher latency, so the

Pentium 4 employs a 400MHz system bus using a 100MHz clock that delivers a data rate of 3.2GB/s to make up for the latency.

Level 3 Cache
eight-way set associative .
line size of 128 bytes. make use of a least recently used replacement

algorithm.
This provides a large on-processor tertiary memory storage area that the processor uses for keeping information nearby. Thus, the contents of the Level 3 cache are faster to access than main memory, but slower than other types of cached

information.

Block Diagram of Pentium 4 Cache Architecture

Thank You