Professional Documents
Culture Documents
K H Wong
khwong@cse 2609-8397,
Room 907 SHB-Engineering building
http://www.cse.cuhk.edu.hk/~khwong/www2/ceng3430/ceng3430.html
Overview
Hardware systems Microprocessors: Arm7 etc Digital systems: e.g. mobile phone, camera chips
Motivations
Design products: Mp3, mp4 players, portable games, mobile phones. Start a business.
Mass products
Mp3, mp4, video players PDA, mobile phones www.wearable-consult.com/images/buergy_hwd.jpg Wearable computer Robots
Novel products
www.cnn.com/.../06/10/mars.rover/index.html
To learn
Methods
Digital Design
Work Flow
Idea generation Drafting on paper Design the chip (use VHDL) Test Manufacturing production line design Quality control
VHDL 0 (v.1b) : Introduction 8
We use
Hardware: FPGA (Field Programmable Gate Array) Software: VHDL (Very-High-Speed-Integrated
IOB=Input/Output block CLB=Configurable Logic block (static ram based) Change the CLBs to get the desired functions
VHDL 0 (v.1b) : Introduction 10
From http://www.alldatasheet.co.kr/datasheetpdf/pdf_kor/49173/XILINX/XCS10-3PC84C.html
CLB
http://www.design-reuse.com/news_img/20100913_1.gif http://pldworld.biz/html/technote/pldesignline/bobz-02.gif
VHDL 0 (v.1b) : Introduction 11
or/and
13
Development cycle
FPGA development
VHDL language
Schematic (diagram)
Schematic / VHDL
1 entity and2 is port (a,b : in std_logic; 2 c : out std_logic); 3 end and2 4 architecture and2_arch of and2 5 begin 6 c <=a and b; 7 end and2_arch
simulation
14
Timing simulation
15
Summary of VHDL
For hardware Design Parallel language (not sequential) Different! (not the same as C++ or Java) VHDL is the industrial standard for CE.
16
1 2 3 4 5 6 7
entity and2 is port (a,b : in std_logic; c : out std_logic); end and2 architecture and2_arch of and2 begin c <=a and b; a b end and2_arch
C<=a and b
The chip
17
18
Apple
IBM
Microsoft
Intel
HP
65.23 99
69.94
43.6
99.87
75.1
63.2 11.46
124.5 14.83
20.43 5.55
14.01 14
Boeing Nestle
Honda Toyota
Ford
HS BC
Len BP ovo
Sony
68.5
125
120
235
128
64.3
126
125
370
166
Profit US Billion
3.3
39
1.39
5.07
6.56
13. 0.2 15 73
20
http://www.tsmc.com
From Wiki: Has the largest asset in Taiwan stock market, World's largest dedicated independent semiconductor foundry. Products: Apple iphone5's A6-cpu
Relation to VHDL
21
From wiki:
Products: the second-largest supplier of mobile telecommunications infrastructure equipment in the world (after Ericsson).
References
See course web page Digital Design Principles and Practices by John F. Wakerly, Prentice Hall (third Edition) 2001 includes Xilinx student edition). http://www.alldatasheet.com/
www.eece.unm.edu/course/ece338/Lectures/ basic-fpga-arch-xilinx.ppt
High-Speed Digital Design: A Handbook of Black Magic by Howard W. Johnson and Martin Graham, Prentice Hall, 1993. Around US$20 dollars.
VHDL 0 (v.1b) : Introduction 23
Tri-state Logic
A revision
24
0 1 0 1
Input
Output enable (OE) Same as Input Output enable (OE)
Output
Output
OE=1, switch close OE=0, switch open
VHDL 0 (v.1b) : Introduction 26
Output enable
0 1 0 1
OE (input) 0 0 1 1
Output
5V Output
27
B Directional control(OE1)
VHDL 0 (v.1b) : Introduction 28
Exercise 0.3 Application 2 of Tri-state logic: Transceivers for I/O data pins
When T =1, A->B; T controls the traffic, when /OE=1, IO pins A,B are disabled Draw the truth table of A,B,/OE,T
/OE
29
A good controller will enable the CPU to read/write RAM, and read ROM
CPU data lines /OE1, T1 transceivers /OE3, T3 /OE2, T2 ROM data transceivers lines
VHDL 0 (v.1b) : Introduction 30
Exercise 0.4 : List OE1,2,3 and T1,2,3 for the followings cases
a) CPU writes to RAM b) CPU reads from ROM c) CPU reads from RAM
CPU data lines A transceivers /OE1, T1 B /OE3, T3
Input_B OE
VHDL 0 (v.1b) : Introduction 32
Exercise 0.6
5V 10K
Output
33