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VHDL 0 Introduction to VHDL

K H Wong
khwong@cse 2609-8397,
Room 907 SHB-Engineering building
http://www.cse.cuhk.edu.hk/~khwong/www2/ceng3430/ceng3430.html

VHDL 0 (v.1b) : Introduction

A quick run through


Overview

VHDL 0 (v.1b) : Introduction

Overview

What is VHDL used for?


To design

Hardware systems Microprocessors: Arm7 etc Digital systems: e.g. mobile phone, camera chips

VHDL 0 (v.1b) : Introduction

Motivations

Learn to design digital systems. Provide knowledge for you to :

Design products: Mp3, mp4 players, portable games, mobile phones. Start a business.

VHDL 0 (v.1b) : Introduction

Examples of digital system design

Mass products

Mp3, mp4, video players PDA, mobile phones www.wearable-consult.com/images/buergy_hwd.jpg Wearable computer Robots

Novel products

www.cnn.com/.../06/10/mars.rover/index.html

VHDL 0 (v.1b) : Introduction

To learn

Design digital processing components using programmable logic

Methods

(a) Schematic, (b) Language (VHDL--Very-High-Speed-IntegratedCircuits Hardware Description Language)

VHDL 0 (v.1b) : Introduction

Digital Design
Work Flow

VHDL 0 (v.1b) : Introduction

Digital Design Work Flow


Idea generation Drafting on paper Design the chip (use VHDL) Test Manufacturing production line design Quality control
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We use
Hardware: FPGA (Field Programmable Gate Array) Software: VHDL (Very-High-Speed-Integrated

Circuits Hardware Description Language)

VHDL 0 (v.1b) : Introduction

Hardware: FPGA Field Programmable Gate Array

IOB=Input/Output block CLB=Configurable Logic block (static ram based) Change the CLBs to get the desired functions
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From http://www.alldatasheet.co.kr/datasheetpdf/pdf_kor/49173/XILINX/XCS10-3PC84C.html

Inside a CLB (Configurable Logic block )

CLB

http://www.design-reuse.com/news_img/20100913_1.gif http://pldworld.biz/html/technote/pldesignline/bobz-02.gif
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Software: to program an FPGA


Use a language VHDL (for modules) Use a schematic (merge modules)
1 entity and2 is port (a,b : in std_logic; 2 c : out std_logic); 3 end and2 4 architecture and2_arch of and2 5 begin 6 c <=a and b; 7 end and2_arch

or/and

VHDL 0 (v.1b) : Introduction

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Development cycle
FPGA development

VHDL language

Schematic (diagram)

Schematic / VHDL

1 entity and2 is port (a,b : in std_logic; 2 c : out std_logic); 3 end and2 4 architecture and2_arch of and2 5 begin 6 c <=a and b; 7 end and2_arch

simulation

VHDL 0 (v.1b) : Introduction

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Timing simulation

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Summary of VHDL

For hardware Design Parallel language (not sequential) Different! (not the same as C++ or Java) VHDL is the industrial standard for CE.

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An example: And gate in VHDL


1 2 3 4 5 6 7

entity and2 is port (a,b : in std_logic; c : out std_logic); end and2 architecture and2_arch of and2 begin c <=a and b; a b end and2_arch
C<=a and b

The chip

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Computer Engineering Market


and VHDL

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Wiki: 20092,589.6,16,000 http://money.163.com 500 (2011-08-25)

Major high-tech companies , a comparison in 2011 (from wiki)


Company

Apple

IBM

Microsoft

Intel

HP

TSMC (largest asset in Taiwan stock market) 13.98

Huawei (Telecom equipmt, China large private company) 21.8

Revenue US Billion Asset Profit US Billion

65.23 99

69.94

43.6

99.87

75.1

113.5 108.7 23.15

63.2 11.46

124.5 14.83

20.43 5.55

Not known 2.67


19

14.01 14

VHDL 0 (v.1b) : Introduction

Major companies , a comparison in 2011 (from wiki)


Company

Boeing Nestle

Honda Toyota

Ford

HS BC

Len BP ovo

Sony

Revenue US Billion Asset

68.5

125

120

235

128

98. 21. 9 59 24 54 10. 71

308 86.64 .9 272 155.9 .2 4 3.3 2.96

64.3

126

125

370

166

Profit US Billion

3.3

39

1.39

5.07

6.56

13. 0.2 15 73

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TSMC (Taiwan Semicon. Manufacturing Comp.)

http://www.tsmc.com

From Wiki: Has the largest asset in Taiwan stock market, World's largest dedicated independent semiconductor foundry. Products: Apple iphone5's A6-cpu

Relation to VHDL

Design ideaWrite VHDL TSMC chips

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Huawei Technologies Co. Ltd http://www.huawei.com/en/

From wiki:

Telecom equipment manufacture China large private company--http://money.163.com 500 (2011-08-25)

Products: the second-largest supplier of mobile telecommunications infrastructure equipment in the world (after Ericsson).

Relation with VHDL (_ http://download.ourdev.cn/bbs_upload84930 6/files_14/ourdev_437357.pdf


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References

See course web page Digital Design Principles and Practices by John F. Wakerly, Prentice Hall (third Edition) 2001 includes Xilinx student edition). http://www.alldatasheet.com/

www.eece.unm.edu/course/ece338/Lectures/ basic-fpga-arch-xilinx.ppt
High-Speed Digital Design: A Handbook of Black Magic by Howard W. Johnson and Martin Graham, Prentice Hall, 1993. Around US$20 dollars.
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Tri-state Logic
A revision

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Appendix 1:Tri-state logic **At float the wire is cut


Input

OE (input) Output 0 0 1 1 Z(Float) Z(Float) 0 1


Output
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0 1 0 1

Input Output enable (OE)

Tria-state equivalent circuit

Input
Output enable (OE) Same as Input Output enable (OE)

Output

Output
OE=1, switch close OE=0, switch open
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Exercise0.1:Tri-state logic with pull up resistor

**At float the wire is cut


Input1

Output enable

0 1 0 1

OE (input) 0 0 1 1

Output

10K Input1 Output enable (OE)

5V Output

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Exercise 0.2 Application 1 of Tri-state logic: Input/Output pin


OE1 controls the traffic. Draw the truth table of A,B,OE1


A

B Directional control(OE1)
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Exercise 0.3 Application 2 of Tri-state logic: Transceivers for I/O data pins

When T =1, A->B; T controls the traffic, when /OE=1, IO pins A,B are disabled Draw the truth table of A,B,/OE,T

/OE

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All data-lines are transceiver buffers


A good controller will enable the CPU to read/write RAM, and read ROM
CPU data lines /OE1, T1 transceivers /OE3, T3 /OE2, T2 ROM data transceivers lines
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RAM data lines transceivers

Exercise 0.4 : List OE1,2,3 and T1,2,3 for the followings cases

a) CPU writes to RAM b) CPU reads from ROM c) CPU reads from RAM
CPU data lines A transceivers /OE1, T1 B /OE3, T3

RAM B data A lines transceivers

/OE2, T2 ROM data transceivers lines B A


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Exercise 0.5 Application 3 of Tri-state logic:


Selection of control signal (resolved logic)

Output will depend on Input_A or Input_B, depending on OE


Input_A Output

Input_B OE
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Exercise 0.6

Draw the truth table of OE1, OE2, output of this circuit


0V OE1 0V OE2
VHDL 0 (v.1b) : Introduction

5V 10K

Output

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