Professional Documents
Culture Documents
CPU for Computers No RAM, ROM, I/O on CPU chip itself ExampleIntels x86, Motorolas 680x0
Data Bus
RAM
ROM
I/O Port
Timer
Microcontroller :
A smaller computer On-chip RAM, ROM, I/O ports... ExampleMotorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X
CPU
RAM ROM
A single chip
I/O Port
Serial Timer COM Port Microcontroller
Embedded System
Embedded system means the processor is embedded into that application. An embedded product uses a microprocessor or microcontroller to do one task only. In an embedded system, there is only one application software that is typically burned into ROM. Exampleprinter, keyboard, video game player
2.
3.
meeting the computing needs of the task efficiently and cost effectively speed, the amount of ROM and RAM, the number of I/O ports and timers, size, packaging, power consumption easy to upgrade cost per unit availability of software development tools assemblers, debuggers, C compilers, emulator, simulator, technical support wide availability and reliable sources of the microcontrollers.
On-chip RAM
Timer 1 Timer 0
Counter Inputs
CPU
Serial Port
OSC
Bus Control
4 I/O Ports
P0 P1 P2 P3
TxD RxD
Address/Data
Feature ROM (program space in bytes) RAM (bytes) Timers I/O pins Serial port Interrupt sources
8051 4K 128 2 32 1 6
8052 8K 256 3 32 1 8
8031 0K 128 2 32 1 6
PDIP/Cerdip
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T1)P3.5 (WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
8051 (8031)
Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8)
Vccpin 40 Vcc provides supply voltage to the chip. The voltage source is +5V. GNDpin 20ground XTAL1 and XTAL2pins 19,18 These 2 pins provide external clock. Way 1using a quartz crystal oscillator Way 2using a TTL oscillator
RSTpin 9reset It is an input pin and is active highnormally low. The high pulse must be high at least 2 machine cycles. It is a power-on reset. Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost. Reset values of some 8051 registers
/EApin 31external access There is no on-chip ROM in 8031 and 8032 . The /EA pin is connected to GND to indicate the code is stored externally. /PSEN ALE are used for external ROM. For 8051, /EA pin is connected to Vcc. / means active low. /PSENpin 29program store enable This is an output pin and is connected to the OE pin of the ROM in 8031 based systems
ALEpin 30address latch enable It is an output pin and is active high. 8051 port 0 provides both address and data. The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. I/O port pins The four ports P0, P1, P2, and P3. Each port uses 8 pins. All I/O pins are bi-directional.
Using a quartz crystal oscillator We can observe the frequency on the XTAL2 pin. C2 XTAL2 30pF C1 XTAL1 30pF GND
Find the machine cycle for (a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz. Solution:
(a) 11.0592 MHz / 12 = 921.6 kHz; machine cycle = 1 / 921.6 kHz = 1.085 s (b) 16 MHz / 12 = 1.333 MHz; machine cycle = 1 / 1.333 MHz = 0.75 s
Vcc
19
Vcc
31 10 uF 30 pF
EA/VPP X1
X2 RST 9 8.2 K
The 8051 has four I/O ports Port 0 pins 32-39P0P0.0P0.7 Port 1pins 1-8 P1P1.0P1.7 Port 2pins 21-28P2P2.0P2.7 Port 3pins 10-17P3P3.0P3.7 Each port has 8 pins. Named P0.X X=0,1,...,7, P1.X, P2.X, P3.X ExP0.0 is the bit 0LSBof P0 ExP0.7 is the bit 7MSBof P0 These 8 bits form a byte. Each port can be used as input or output (bi-direction).
Registers
A B R0 R1 R2 R3 R4 R5 R6 Some 8051 16-bit Register PC PC DPTR DPH DPL
; dest = source ;A=72H ;A=r OR 72H ;R4=62H ;B=the content of F9th byte of RAM
MOV DPTR,#7634H MOV DPL,#34H MOV DPH,#76H MOV P1,A Note 1: MOV A,#72H After instruction MOV 8086 MOV MOV MOV MOV Note 2: MOV ;mov A to port 1
MOV A,72H A,72H the content of 72th byte of RAM will replace in Accumulator. 8051 MOV MOV MOV
MOV
ADD
A, Source
;A=A+SOURCE
ADD
ADD ADD ADD
A,#6
A,R6 A,6 A,0F3H
;A=A+6
;A=A+R6 ;A=A+[6] or A=A+R6 ;A=A+[0F3H]
SETB CLR
SETB SETB SETB SETB SETB
Note:
bit bit
; bit=1 ; bit=0
; CY=1 ;bit 0 from port 0 =1 ;bit 7 from port 3 =1 ;bit 2 from ACCUMULATOR =1 Bit Addressable ;set high D5 of RAM loc. 20h
Page 359,360
CLR instruction is as same as SETB i.e: CLR C ;CY=0 But following instruction is only for CLR: CLR A ;A=0
SUBB
SETB C SUBB
A,source ;A=A-source-CY
;CY=1 A,R5 ;A=A-R5-1
ADC
SETB C ADC A,R5
A,source ;A=A+source+CY
;CY=1 ;A=A+R5+1
DEC INC
INC DEC DEC
byte byte
R7 A 40H
;byte=byte-1 ;byte=byte+1
; [40]=[40]-1
CPL
Example: MOV L01: CPL MOV ACALL SJMP
;1s complement
A,#55H ;A=01010101 B A P1,A DELAY L01
CALL
EDITOR PROGRAM Myfile.asm ASSEMBLER PROGRAM Myfile.lst Other obj file Myfile.obj LINKER PROGRAM
Myfile.abs
OH PROGRAM Myfile.hex
8k
0000H
32k
1FFFH
8752 AT89C52
7FFFH
30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H Register Bank 2 Register Bank 1 (Stack) Register Bank 0 Register Bank 3
PSW Register
CY AC F0 RS1 RS0 OV -P
Carry flag
PSW.7
CY
Auxiliary carry flag Available to the user for general purpose Register Bank selector bit 1 Register Bank selector bit 0 Overflow flag User define bit Parity flag Set/Reset odd/even parity
RS1 0 0 1 1 RS0 0 1 0 1 Register Bank 0 1 2 3
AC -RS1 RS0 OV -P
Address 00H-07H 08H-0FH 10H-17H 18H-1FH
Note: X can be 0 or 1
Example: MOV A,#88H ADD A,#93H 88 +93 ---11B CY=1 AC=0 10001000 +10010011 -------------00011011 P=0
Example: MOV A,#38H ADD A,#2FH 38 +2F ---67 CY=0 AC=1 00111000 +00101111 -------------01100111 P=1
Example :
EQU
30
R0,Num DPTR,#data1 100H db IRAN
Rn, A A, Rn DPL, R6
;n=0,..,7
MOV MOV
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode, it is most often used to access RAM loc. 30 7FH. MOV MOV MOV MOV R0, 40H 56H, A A, 4 6, 2
it is important to note that when using direct addressing any instruction which refers to an address between 00h and 7Fh is referring to Internal Memory. Any instruction which refers to an address between 80h and FFh is referring to the SFR control registers that control the 8051 microcontroller itself.
In this mode, register is used as a pointer to the data. A,@Ri @R1,B ; move content of RAM loc.Where address is held by Ri into A ( i=0 or 1 )
MOV MOV
In other word, the content of register R0 or R1 is sources or target in MOV, ADD and SUBB insructions. Example: Write a program to copy a block of 10 bytes from RAM location sterting at 37h to RAM location starting at 59h. Solution: MOV R0,37h MOV R1,59h MOV R2,10 L1: MOV A,@R0 MOV @R1,A INC R0 INC R1 DJNZ R2,L1
; source pointer ; dest pointer ; counter
jump
Indirect addressing always refers to Internal RAM; it never refers to an SFR. using this we can not write data to serial port by making use of its SFR address which is 99h.
This mode is widely used in accessing data elements of look-up table entries located in the program (code) space ROM at the 8051
MOVC A,@A+DPTR A= content of address A +DPTR from ROM Note: Because the data elements are stored in the program (code ) space ROM of the 8051, it uses the instruction MOVC instead of MOV. The C means code.
Example: Assuming that ROM space starting at 250h contains Hello., write a program to transfer the bytes into RAM locations starting at 40h. Solution: ORG 0 MOV DPTR,#MYDATA MOV R0,#40H L1:CLR A MOVC A,@A+DPTR JZ L2 MOV @R0,A INC DPTR INC R0 SJMP L1 L2:SJMP L2 ;------------------------------------ORG 250H MYDATA: DB Hello,0
END Notice the NULL character ,0, as end of string and how we use the JZ instruction to detect that.
Example: Write a program to get the x value from P1 and send x2 to P2, continuously . Solution: ORG 0 MOV DPTR, #TAB1 MOV A,#0FFH MOV P1,A L01: MOV A,P1 MOVC A,@A+DPTR MOV P2,A SJMP L01 ;---------------------------------------------------ORG 300H TAB1: DB 0,1,4,9,16,25,36,49,64,81
END
Exercise:
Write a program to add n 16-bit number. Get n from port 1. And sent Sum to LCD a) in hex b) in decimal Write a program to subtract P1 from P0 and send result to LCD
(Assume that ACAL DISP display A to LCD )
;A=2, B=5
The register used to access the stack is called SP (stack pointer) register. The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07.
2FH
Bit-Addressable RAM
20H 1FH 18H 17H 10H 0FH 08H 07H 00H
Example: MOV MOV MOV PUSH PUSH PUSH R6,#25H R1,#12H R4,#0F3H 6 1 4
SP=08H
SP=09H
SP=08H
DJNZ:
Write a program to clear ACC, then add 3 to the accumulator ten time
Solution:
MOV MOV AGAIN: ADD DJNZ MOV A,#0; R2,#10 A,#03 R2,AGAING ;repeat until R2=0 (10 times) R5,A
JZ
JNZ
JB
JNB JBC
Jump if bit=1
Jump if bit=0 Jump if bit=1 and clear bit
Exercise: Write a program that compare R0,R1. If R0>R1 then send 1 to port 2, else if R0<R1 then send 0FFh to port 2, else send 0 to port 2.
Another control transfer instruction is the CALL instruction, which is used to call a subroutine.
LCALL(long call) In this 3-byte instruction, the first byte is the opcode an the second and third bytes are used for the address of target subroutine. Therefore, LCALL can be used to call subroutines located anywhere within the 64K byte address space of the 8051.
Port 1 is denoted by P1. P1.0 ~ P1.7 We use P1 as examples to show the operations on ports. P1 as an output port (i.e., write CPU data to the external pin) P1 as an input port (i.e., read pin data into CPU bus)
Read latch
TB2
Vcc
Load(L1)
P1.X
Clk Q
P1.X pin M1
P0.x
8051 IC
Each pin of I/O ports Internal CPU buscommunicate with CPU A D latch store the value of this pin D latch is controlled by Write to latch Write to latch1write data into the D latch 2 Tri-state buffer TB1: controlled by Read pin Read pin1really read the data present at the pin TB2: controlled by Read latch Read latch1read value from internal latch A transistor M1 gate Gate=0: open Gate=1: close
Output
Input
Low
Highimpedance (open-circuit)
Read latch
TB2
Vcc
Load(L1) 2. output pin is
Vcc 1 0
M1
P1.X
Clk Q
P1.X pin
output 1
8051 IC
Read latch
TB2
Vcc
Load(L1) 2. output pin is
ground 0 1
M1
P1.X
Clk Q
P1.X pin
output 0
8051 IC
Send data to Port 1 MOV A,#55H MOV P1,A ACALL DELAY CPL A SJMP BACK
BACK:
When reading ports, there are two possibilities Read the status of the input pin. from external pin value MOV A, PX JNB P2.1, TARGET ; jump if P2.1 is not set JB P2.1, TARGET ; jump if P2.1 is set Figures C-11, C-12 Read the internal latch of the output port. ANL P1, A ; P1 P1 AND A ORL P1, A ; P1 P1 OR A INC P1 ; increase P1 Figure C-17 Table C-6 Read-Modify-Write Instruction (or Table 8-5)
Read latch 1. write a 1 to the pin MOV P1,#0FFH Internal CPU bus TB2
Vcc
Load(L1) 1 1
Q
P1.X
P1.X pin
Write to latch
Clk
M1
TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1 8051 IC
Read latch 1. write a 1 to the pin MOV P1,#0FFH Internal CPU bus TB2
Vcc
Load(L1) 1 0
Q
P1.X
P1.X pin
Write to latch
Clk
M1
TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1 8051 IC
In order to make P1 an input, the port must be programmed by writing 1 to all the bit. MOV MOV MOV MOV SJMP A,#0FFH P1,A A,P1 P2,A BACK ;A=11111111B ;make P1 an input port ;get data from P0 ;send data to P2
BACK:
Following are instructions for reading external pins of ports: Mnemonics MOV A,PX Examples MOV A,P2 Description Bring into A the data at P2 pins
JNB PX.Y,..
JB PX.Y,.. MOV C,PX.Y
JNB P2.1,TARGET
JB P1.3,TARGET MOV C,P2.4
Exclusive-or the Port 1 MOV P1,#55H ;P1=01010101 ORL P1,#0F0H ;P1=11110101 1. The read latch activates TB2 and bring the data from the Q latch into CPU. Read P1.0=0 2. CPU performs an operation. This data is ORed with bit 1 of register A. Get 1. 3. The latch is modified. D latch of P1.0 has value 1. 4. The result is written to the external pin. External pin (pin 1: P1.0) has value 1.
1. Read pin=0 Read latch=1 Write to latch=0 (Assume P1.X=0 initially) Read latch TB2 2. CPU compute P1.X OR 1 0 Internal CPU bus 1 Write to latch 3. write result to latch Read pin=0 Read latch=0 Write to latch=1 Load(L1) 0 1 4. P1.X=1 P1.X pin
Vcc
Q
P1.X
0 M1
Clk
8051 IC
Read-modify-write Instructions Table C-6 This features combines 3 actions in a single instruction 1. CPU reads the latch of the port 2. CPU perform the operation 3. Modifying the latch 4. Writing to the pin Note that 8 pins of P1 work independently.
Exclusive-or the Port 1 MOV P1,#55H ;P1=01010101 AGAIN: XOR P1,#0FFH ;complement ACALL DELAY SJMP AGAIN Note that the XOR of 55H and FFH gives AAH. XOR of AAH and FFH gives 55H. The instruction read the data in the latch (not from the pin). The instruction result will put into the latch and the pin.
Mnemonics
ANL ORL XRL JBC PX.Y, TARGET CPL INC DEC DJNZ PX, TARGET
Example
ANL P1,A ORL P1,A XRL P1,A JBC P1.1, TARGET CPL P1.2 INC P1 DEC P1 DJNZ P1,TARGET
MOV PX.Y,C
CLR PX.Y SETB PX.Y
MOV P1.2,C
CLR P1.3 SETB P1.4
How to write the data to a pin How to read the data from the pin Read the value present at the external pin. Why we need to set the pin first Read the value come from the latchnot from the external pin. Why the instruction is called read-modify write?
P1, P2, and P3 have internal pull-up resisters. P1, P2, and P3 are not open drain. P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051. P0 is open drain. Compare the figures of P1.X and P0.X. However, for a programmer, it is the same to program P0, P1, P2 and P3. All the ports upon RESET are configured as output.
Read latch
TB2
P1.X
Clk Q
P0.X pin M1
P1.x
8051 IC
P0 is an open drain. Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips. When P0 is used for simple data I/O we must connect it to external pull-up resistors. Each pin of P0 must be connected externally to a 10K ohm pull-up resistor. With external pull-up resistors connected upon reset, port 0 is configured as an output port.
Vcc
10 K
P0.0 DS5000 P0.1 P0.2 8751 P0.3 P0.4 8951 P0.5 P0.6 P0.7
Port 0
When connecting an 8051/8031 to an external memory, the 8051 uses ports to send addresses and read instructions. 8031 is capable of accessing 64K bytes of external memory. 16-bit addressP0 provides both address A0-A7, P2 provides address A8-A15. Also, P0 provides data lines D0-D7. When P0 is used for address/data multiplexing, it is connected to the 74LS373 to latch the address. There is no need for external pull-up resistors as shown in Chapter 14.
G D
74LS373
OE OC A0 A7
D0 EA P2.0 P2.7 D7
A8 A15
8051
ROM
A7 Address D0
EA P2.0 P2.7
D7
A8 A12
8051
ROM
74LS373
OE OC A0 A7
Address
8051
ROM
The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.
When ALE=0, P0 provides data D0-D7. When ALE=1, P0 provides address A0-A7. The reason is to allow P0 to multiplex address and
data.
Port 2 does not need any pull-up resistors since it already has pull-up resistors internally. In an 8031-based system, P2 are used to provide address A8-A15.
Port 3 does not need any pull-up resistors since it already has pull-up resistors internally. Although port 3 is configured as an output port upon reset, this is not the way it is most commonly used. Port 3 has the additional function of providing signals. Serial communications signalRxD, TxDChapter 10 External interrupt/INT0, /INT1Chapter 11 Timer/counterT0, T1Chapter 9 External memory accesses in 8031-based system/WR, /RDChapter 14
P3 Bit
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
Function
RxD TxD INT0 INT1 T0 T1 WR RD
Pin
10 11 12 13 14 15 16 17
Timer 0 registers
TL0 ( timer 0 low byte ) TH0 ( timer 0 high byte )
Timer 1 registers
TL1 ( timer 1 low byte ) TH1 ( timer 1 high byte )
TF0/TF1:
Timer0/1 overflow flag is set when the timer counter overflows, reset by program
TR0/TR1:
IE0/IE1:
Timer0/1 run control bit is set to start, reset to stop the timer0/1
External interrupt 9/1 edge detected flag1 is set when a falling edge interrupt on the external port 0/1, reset(cleared) by hardware itself for falling edge transition-activated INT; Reset by code for low level INT. External interrupt type (1: falling edge triggered, 0 low level triggered)
IT0/IT1
Mode 0 Programming0
Mode 0 works like mode 1 13-bit timer instead of 16bit 13-bit counter hold values 0000 to 1FFFH when the timer reaches its maximum of 1FFFH, it rolls over to 0000, and TF is set
Mode 1 programming
16-bit timer, values of 0000 to FFFFH TH and TL are loaded with a 16-bit initial value timer started by "SETB TR0" for Timer 0 and "SETB TR1"
for Timer l timer count ups until it reaches its limit of FFFFH rolls over from FFFFH to 0000H sets TF (timer flag) when this timer flag is raised, can stop the timer with "CLR TR0" or "CLR TR1 after the timer reaches its limit and rolls over, the registers TH and TL must be reloaded with the original value and TF must be reset to 0
Create a square wave of 50% duty cycle (with equal portions high and low) on the P1.5 bit. Timer 0 is used to generate the time delay
XTAL = 11.0592 MHz (12MHz) divide the desired time delay by 1.085ms (1ms) to get n 65536 n = N
Create a square wave of 50% duty cycle (with equal portions high and low) on the P1.5 bit. Timer 0 is used to generate the time delay
Assuming XTAL = 11.0592 MHz, write a program to generate a square wave of 50 Hz frequency on pin P2.3.
T = 1/50 Hz = 20 ms 1/2 of it for the high and low portions of the pulse = 10 ms 10 ms / 1.085 us = 9216 65536 - 9216 = 56320 in decimal = DC00H TL = 00 and TH = DCH The calculation for 12MHz crystal uses the same steps
Mode 2 programming
Mode 2 programming
8-bit timer, allows values of 00 to FFH TH is loaded with the 8-bit value a copy is given to TL timer is started by ,"SETB TR0" or "SETB TR1 starts to count up by incrementing the TL register counts up until it reaches its limit of FFH when it rolls over from FFH to 00, it sets high TF TL is reloaded automatically with the value in TH To repeat, clear TF mode 2 is an auto-reload mode
load TMOD, select mode 2 load the TH start timer monitor the timer flag (TF) with "JNB get out of the loop when TF=1 clear TF go back to Step 4 since mode 2 is auto-reload
Assuming that XTAL = 11.0592 MHz, find (a) the frequency of the square wave generated on pin P1.0 and (b) the smallest frequency achievable in this program, and the TH value to do that.
8051 Interrupts
An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service. Interrupts vs. Polling A single microcontroller can serve several devices. There are two ways to do that:
interrupts polling.
The program which is associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler.
Finish current instruction and saves the PC on stack. Jumps to a fixed location in memory depend on type of interrupt Starts to execute the interrupt service routine until RETI (return from interrupt) Upon executing the RETI the microcontroller returns to the place where it was interrupted. Get pop PC from stack
Reset Timer 0 overflow Timer 1 overflow External Interrupt 0 External Interrupt 1 Serial Port events (buffer full, buffer empty, etc)
Each interrupt has a specific place in code memory where program execution (interrupt service routine) begins.
External Interrupt 0: 0003h Timer 0 overflow: 000Bh External Interrupt 1: 0013h Timer 1 overflow: 001Bh Serial : 0023h Timer 2 overflow(8052+) 002bh
All interrupt are disabled after reset We can enable and disable them bye IE
by bit operation Recommended in the middle of program SETB EA SETB IE.7 SETB ET0 SETB IE.1 SETB ET1 SETB IE.3 SETB EX0 SETB IE.0 SETB EX1 SETB IE.2 SETB ES SETB IE.4 by mov instruction Recommended in the first of program
ORG 0030H MAIN: MOV TMOD,#02H MOV TH0,#-50 SETB TR0 MOV IE,#82H SJMP $ END
Write a program using interrupts to simultaneously create 7 kHz and 500 Hz square waves on P1.7 and P1.6.
8051 P1.7
143s 71s
2ms
P1.6
1ms
Solution
ORG LJMP ORG LJMP ORG LJMP ORG MOV MOV SETB SETB MOV MOV SJMP CPL RETI CLR MOV MOV SETB CPL RETI END 0 MAIN 000BH T0ISR 001BH T1ISR 0030H TMOD,#12H TH0,#-71 TR0 TF1 IE,#8AH IE,#8AH $ P1.7 TR1 TH1,#HIGH(-1000) TL1,#LOW(-1000) TR1 P1.6
8051 P1.7
143s 71s
MAIN:
2ms
P1.6
1ms
T0ISR: T1ISR:
Notice that
There is no need for a CLR TFx instruction in
Notice that
We must reload timer in mode 1 There is no need on mode 2 (timer auto reload)
By low nibble of Timer control register TCON IE0 (IE1): External interrupt 0(1) edge flag.
set by CPU when external interrupt edge (H-to-L) is detected.
Does not affected by H-to-L while ISR is executed(no int on int) Cleared by CPU when RETI executed. does not latch low-level triggered interrupt
IE1
(LSB) IT0
External Interrupts
0003
IE0 (TCON.3)
Edge-triggered
0013
Edge-triggered
ORG 0013H SETB P1.1 MOV R0,200 WAIT: DJNZ R0,WAIT CLR P1.1 RETI
;
ORG 30H MAIN: SETB IT1 ;on negative edge of INT1 MOV IE,#10000100B WAIT2: SJMP WAIT2 END
x1isr:
Org 0030h Main: mov ie,#85h Setb it0 Setb it1 Setb p1.7 Jb p3.2,skip Clr p1.7 Skip: Sjmp $ end
What if two interrupt sources interrupt at the same time? The interrupt with the highest PRIORITY gets serviced first. All interrupts have a power on default priority order.
1. External interrupt 0 (INT0) 2. Timer interrupt0 (TF0) 3. External interrupt 1 (INT1) 4. Timer interrupt1 (TF1)
---
---
PT2
PS
PT1
PX1
PT0
PX0
IP.7: reserved IP.6: reserved IP.5: timer 2 interrupt priority bit(8052 only) IP.4: serial port interrupt priority bit IP.3: timer 1 interrupt priority bit IP.2: external interrupt 1 priority bit IP.1: timer 0 interrupt priority bit IP.0: external interrupt 0 priority bit
--
---
PT2
PS
PT1
PX1
PT0
PX0
---
---
PT2
PS
PT1
PX1
PT0
PX0
A high-priority interrupt can interrupt a low-priority interrupy All interrupt are latched internally Low-priority interrupt wait until 8051 has finished servicing the high-priority interrupt