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Cc thanh ghi c bn
T chc b nh d liu
B nh d liu
64 KB khng gian nh C th nh byte hoc word 16-bit t nh word
Bn d liu nh*
Cc nhm cu lnh
Cc cu lnh MOVE Cc cu lnh MATH Cc cu lnh LOGIC Cc cu lnh ROTATE/SHIFT Cc cu lnh thao tc vi BIT Cc cu lnh COMPARE/SKIP Cc cu lnh PROGRAM/FLOW Cc cu lnh SHADOW/STACK Cc cu lnh CONTROL Cc cu lnh DSC
Cc ch nh a ch
Cc ch nh a ch :
C hu NOP, RESET, PUSH, POP, Bng ch Thanh ghi Mng thanh ghi W (16x16 Bit) Trc tip b nh Gin tip thanh ghi Truy cp hu nh ton b 64KB
With pre-inc or pre-dec With post-inc or post-dec With signed literal offset
Interrupts
Quyn u tin v Vector ngt
C hn 45 ngun ngt (khng bao gm traps and reset) C 7 mc u tin ngt
Interrupts
Stack ngt c b tr trn SRAM vi s t ng kim tra bin gii S xp lng ngt Ngt c mc u tin cao hn c th ngt ngt c mc u tin thp hn Cu lnh DISI c th treo ngt trong N chu k
Mt cch nhanh chng bo v nhng on code nguy kch Cm cc ngt c mc u tin t 0 6
Traps(Gi CPU)
Oscillator Failure Trap
Xung nhp chnh b sai (dng dao ng trong RC)
Reset h thng
Reset khi bt ngun
Thi gian tr c th lp trnh : 0, 4, 16, 64 ms
MCLR (External Reset Pin) Thc hin cu lnh Reset Watchdog Timer (WDT) Reset
Thc hin t chnh dao ng RC ca n Thi gian gii hn : 2ms 16s
Ngun xung
Sleep mode :
CPU v xung h thng u dng Ngoi vi cng b dng Hot ng tr li : WDT, thay i tn hiu vo chn, chn ngt ngoi, reset, hoc s kin ngoi vi no
Analog Comparator
Mt s c im :
chnh xc +/- 1% ( trong di in p Vdd ) 0 1,2V Ref or Avdd/2 or ngun chun bn ngoi 1024 bc ( i.e. 1,2mv, 2,4mv, .., 1,2V) Tr so snh : ~20 ns
Analog Comparator
Mi b so snh tng t u c 2 thanh ghi iu khin :
ADC
10 bit , chnh xc +/- 1 bit 2 triu ln trch mu/ 1s (2 MSPS) 6 12 knh u vo Di u vo tng t : 0 5V 4 u vo K Sample/Hold (S/H)
u vo 2 v 4 c th lm vic ng thi
S hot ng ca ADC
S bin i lun din ra trong mt cp u vo tng t (AN0,AN1), (AN2,AN3) , Mi cp miu t in p v dng in o lng Yu cu ngt c to ra trn mt cp c bn. Yu cu ngt c th c to ra khi hon thnh ln bin i th 1 hoc th 2 ca cp Mi chn u vo tng t u c lin kt vi thanh ghi d liu u ra. B m d liu( cc thanh ghi) th khng thc hin nh FIFO. Chng c s hu duy nht bi mi u vo
S khi ca ADC
Thanh ghi trng thi ch cho bit cp no bin i xong (p = pair) Nu chn EIE = 1 th ngt c th c to ra trc khi chn PxRDY tng ng c lp = 1
Cp u vo ADC
Mi cp u vo c thanh ghi iu khin v trng thi 8 bit Mi thanh ghi ADCPCx iu khin v ch trng thi ca 2 cp u vo
Cc ch PWM
Chun ( Standard) B, b xung (Complementary) y ko ( push pull ) Nhiu pha ( Multi phase ) Pha c th thay i ( Variable phase ) Current reset Current limit
Part VI : Mch np
Mch np PG2C
Np qua cng ni tip S dng chng trnh np winpic800 S dng phng php np ICSP ( In Circuit Serial Programming ) Khng c kh nng debug trn bo Rt n gin
MPLAB
Khi vit chng trnh cho dsPIC, ta s dng mi trng MPLAB. Nhiu thng tin thit lp cho cc cng vic lin quan c t trc trong MPLAB gip qun l c vic vit chng trnh, m phng, np chng trnh vo chip mt cch thng nht Trong mi trng MPLAB ph bin s dng hai ngn ng
ASM : ASM30 . C : C30, CCS