Digital Integrated Circuits: A Design Perspective

Digital Integrated Circuits
2nd
Interconnect
Digital Integrated
Circuits
A Design Perspective
Coping with
Interconnect
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
December 15, 2002
2nd
Interconnect
Impact of Interconnect Parasitics
Reduce Robustness
Affect Performance
Increase delay
Increase power dissipation
Classes of Parasitics
Capacitive
Resistive
Inductive
2nd
Interconnect
INTERCONNECT
2nd
Interconnect
Capacitive Cross Talk
X
Y
V
X
C
XY
C
Y
2nd
Interconnect
Dynamic Node
3 x 1 m overlap: 0.19 V disturbance
C
Y
C
XY
V
DD
PDN
CLK
CLK
In
1
In
2
In
3
Y
X
2.5 V
0 V
2nd
Interconnect
Driven Node
t
XY
= R
Y
(C
XY
+C
Y
)
Keep time-constant smaller than rise time
V (Volt)
0
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
1 0.8 0.6
t (nsec)
0.4 0.2
X
Y
V
X
R
Y
C
XY
C
Y
t
r

2nd
Interconnect
Dealing with Capacitive Cross Talk
Avoid floating nodes
Protect sensitive nodes
Make rise and fall times as large as possible
Differential signaling
Do not run wires together for a long distance
Use shielding wires
Use shielding layers
2nd
Interconnect
Shielding
GND
GND
Shielding
wire
Substrate ( GND )
Shielding
layer
V
DD
2nd
Interconnect
Cross Talk and Performance
C
c

- When neighboring lines
switch in opposite direction of
victim line, delay increases
DELAY DEPENDENT UPON
ACTIVITY IN NEIGHBORING
WIRES
Miller Effect
- Both terminals of capacitor are switched in opposite directions
(0 V
dd
, V
dd
0)
- Effective voltage is doubled and additional charge is needed
(from Q=CV)
2nd
Interconnect
Impact of Cross Talk on Delay
r is ratio between capacitance to GND and to neighbor
2nd
Interconnect
Structured Predictable Interconnect
S
S S V V S
G
S
S
V
G
V
S
S S V V S
G
S
S
V
G
V
Example: Dense Wire Fabric ([Sunil Kathri])
Trade-off:
Cross-coupling capacitance 40x lower, 2% delay variation
Increase in area and overall capacitance
Also: FPGAs, VPGAs
2nd
Interconnect
Interconnect Projections
Low-k dielectrics
Both delay and power are reduced by dropping interconnect
capacitance
Types of low-k materials include: inorganic (SiO
2
), organic
(Polyimides) and aerogels (ultra low-k)
The numbers below are on the
conservative side of the NRTS roadmap
Generation 0.25
m
0.18
m
0.13
m
0.1
m
0.07
m
0.05
m
Dielectric
Constant
3.3 2.7 2.3 2.0 1.8 1.5
c
2nd
Interconnect
Encoding Data Avoids Worst-Case
Conditions
Encoder
Decoder
Bus
In
Out
2nd
Interconnect
Driving Large Capacitances
V
in
V
out
C
L
V
DD
Transistor Sizing
Cascaded Buffers
2nd
Interconnect
Using Cascaded Buffers
C
L
= 20 pF

In Out
1 2 N
0.25 m process
Cin = 2.5 fF
tp0 = 30 ps
F = CL/Cin = 8000
fopt = 3.6 N = 7
tp = 0.76 ns
(See Chapter 5)
2nd
Interconnect
Output Driver Design
Trade off Performance for Area and Energy
Given t
pmax
find N and f
Area

Energy
( )
min min min
1 2
1
1
1
1
... 1 A
f
F
A
f
f
A f f f A
N
N
driver
= + + + + =

( )
2 2 2 1 2
1 1
1
... 1
DD
L
DD i DD i
N
driver
V
f
C
V C
f
F
V C f f f E
= + + + + =

2nd
Interconnect
Delay as a Function of F and N
10
1 3 5 7
Number of buffer stages N
9 11
10,000
1000
100
t
p
/
t
p
0
F
=
100
F
=
1000
F
=
10,000
t
p
/
t
p
0

2nd
Interconnect
Output Driver Design
Transistor Sizes for optimally-sized cascaded buffer t
p
= 0.76 ns
Transistor Sizes of redesigned cascaded buffer t
p
= 1.8 ns
0.25 m process, C
L
= 20 pF
2nd
Interconnect
How to Design Large Transistors
G(ate)
S(ource)
D(rain)
Multiple
Contacts
small transistors in parallel
Reduces diffusion capacitance
Reduces gate resistance
2nd
Interconnect
Bonding Pad Design
Bonding Pad
Out
In
V
DD

GND
1
0
0

m

GND
Out
2nd
Interconnect
ESD Protection
When a chip is connected to a board, there is
unknown (potentially large) static voltage
difference
Equalizing potentials requires (large) charge
flow through the pads
Diodes sink this charge into the substrate
need guard rings to pick it up.
2nd
Interconnect
ESD Protection
Diode
PAD
V
DD
R
D1
D2
X
C
2nd
Interconnect
Chip Packaging
Chip
L
L
Bonding wire
Mounting
cavity
Lead
frame
Pin
Bond wires (~25m) are used
to connect the package to the chip

Pads are arranged in a frame
around the chip

Pads are relatively large
(~100m in 0.25m technology),
with large pitch (100m)

Many chips areas are pad limited
2nd
Interconnect
Pad Frame
Layout Die Photo
2nd
Interconnect
Chip Packaging
An alternative is flip-chip:
Pads are distributed around the chip
The soldering balls are placed on pads
The chip is flipped onto the package
Can have many more pads
2nd
Interconnect
Tristate Buffers
In
En
En
V
DD
Out
Out = In.En + Z.En
V
DD
In
En
En
Out
Increased output drive
2nd
Interconnect
Reducing the swing
t
pHL
= C
L
V
swing
/2
I
av
Reducing the swing potentially yields linear
reduction in delay
Also results in reduction in power dissipation
Delay penalty is paid by the receiver
Requires use of sense amplifier to restore signal
level
Frequently designed differentially (e.g. LVDS)
2nd
Interconnect
Single-Ended Static Driver and
Receiver
C
L
VDD
VDD VDD
driver receiver
VDD
L
VDD
L
In
Out Out
2nd
Interconnect
Dynamic Reduced Swing Network
f In
2
. f In
1
.
f M
2
M
1
M
3
M
4
C
bus
C
out
Bus Out
V
DD
V
DD
V(Volt)
f
V
bus
V
asym
V
sym
2 4 6
time (ns)
8 10 12 0
0.5
1
1.5
2
2.5
0
2nd
Interconnect
INTERCONNECT
2nd
Interconnect
Impact of Resistance
We have already learned how to drive RC
interconnect
Impact of resistance is commonly seen in
power supply distribution:
IR drop
Voltage variations
Power supply is distributed to minimize the IR
drop and the change in current due to
switching of gates
2nd
Interconnect
RI Introduced Noise
M 1
X
I
R 9
R
D V
f
pre
D V
V
DD
V
DD
2 D V 9
I
2nd
Interconnect
19
ASP DAC 2000
Power Dissipation Trends
Power Dissipation Trends
Power consumption is increasing Power consumption is increasing
Better cooling technology needed Better cooling technology needed
Supply current is increasing faster! Supply current is increasing faster!
On On- -chip signal integrity will be a major chip signal integrity will be a major
issue issue
Power and current distribution are critical Power and current distribution are critical
Opportunities to slow power growth Opportunities to slow power growth
Accelerate Accelerate Vdd Vdd scaling scaling
Low dielectrics & thinner (Cu) L o w d i e l e c t r i c s & t h i n n e r ( C u )
interconnect interconnect
SOI circuit innovations SOI circuit innovations
Clock system design Clock system design
micro micro- -architecture architecture
Power Dissipation
0
20
40
60
80
100
120
140
160
EV4 EV5 EV6 EV7 EV8
P
o
w
e
r

(
W
)
0
0.5
1
1.5
2
2.5
3
3.5
V
o
l
t
a
g
e

(
V
)
Supply Current
0
20
40
60
80
100
120
140
EV4 EV5 EV6 EV7 EV8
C
u
r
r
e
n
t

(
A
)
0
0.5
1
1.5
2
2.5
3
3.5
V
o
l
t
a
g
e

(
V
)

2nd
Interconnect
Resistance and the Power
Distribution Problem
Source: Cadence
Requires fast and accurate peak current prediction
Heavily influenced by packaging technology
Before
After
2nd
Interconnect
Power Distribution
Low-level distribution is in Metal 1
Power has to be strapped in higher layers of
metal.
The spacing is set by IR drop,
electromigration, inductive effects
Always use multiple contacts on straps
2nd
Interconnect
Power and Ground Distribution
GND
V
DD
Logic
GND
V
DD
Logic
GND
V
DD
(a) Finger-shaped network (b) Network with multiple supply pins
2nd
Interconnect
3 Metal Layer Approach (EV4)
3rd coarse and thick metal layer added to the
technology for EV4 design
Power supplied from two sides of the die via 3rd metal layer
2nd metal layer used to form power grid
90% of 3rd metal layer used for power/clock routing
Metal 3
Metal 2
Metal 1
Courtesy Compaq
2nd
Interconnect
4 Metal Layers Approach (EV5)
4th coarse and thick metal layer added to the
Power supplied from four sides of the die
Grid strapping done all in coarse metal
90% of 3rd and 4th metals used for power/clock routing
Metal 3
Metal 2
Metal 1
Metal 4
Courtesy Compaq
2nd
Interconnect
2 reference plane metal layers added to the
Solid planes dedicated to Vdd/Vss
Significantly lowers resistance of grid
Lowers on-chip inductance
6 Metal Layer Approach EV6
Metal 4
Metal 2
Metal 1
RP2/Vdd
RP1/Vss
Metal 3
Courtesy Compaq
2nd
Interconnect
Electromigration (1)
Limits dc-current to 1 mA/
m
2nd
Interconnect
Electromigration (2)
2nd
Interconnect
Resistivity and Performance
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
0.5
1
1.5
2
2.5
time (nsec)
v
o
l
t
a
g
e

(
V
)
x= L/10
x = L/4
x = L/2
x= L
Diffused signal
propagation

Delay ~ L
2

C
N-1

C
N

C
2

R
1
R
2

C
1

T
r
V
in
R
N-1
R
N

The distributed rc-line
2nd
Interconnect
The Global Wire Problem
Challenges
No further improvements to be expected after the
introduction of Copper (superconducting, optical?)
Design solutions
Use of fat wires
Insert repeaters but might become prohibitive (power, area)
Efficient chip floorplanning
Towards communication-based design
How to deal with latency?
Is synchronicity an absolute necessity?
( )
out w w d out d w w d
C R C R C R C R T
+ + + =
693 . 0 377 . 0
2nd
Interconnect
Interconnect Projections: Copper
Copper is planned in full sub-0.25
m process flows and large-scale
designs (IBM, Motorola, IEDM97)
With cladding and other effects, Cu
~ 2.2 O-cm vs. 3.5 for Al(Cu)
40% reduction in resistance
Electromigration improvement;
100X longer lifetime (IBM,
IEDM97)
Electromigration is a limiting factor
beyond 0.18 m if Al is used (HP,
IEDM95)
Vias
2nd
Interconnect
Interconnect:
# of Wiring Layers
# of metal layers is steadily increasing due to:
Increasing die size and device count: we need
more wires and longer wires to connect
everything
Rising need for a hierarchical wiring network;
local wires with high density and global wires with
low RC
substrate
poly
M1
M2
M3
M4
M5
M6
T
ins
H
W
S
= 2.2
O-cm
0.25 m wiring stack
Minimum Widths (Relative)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.0 0.8 0.6 0.35 0.25
M5
M4
M3
M2
M1
Poly
Minimum Spacing (Relative)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
1.0 0.8 0.6 0.35 0.25
M5
M4
M3
M2
M1
Poly
2nd
Interconnect
Diagonal Wiring
y
x
destination
Manhattan
source
diagonal
20+% Interconnect length reduction
Clock speed
Signal integrity
Power integrity
15+% Smaller chips
plus 30+% via reduction
Courtesy Cadence X-initiative
2nd
Interconnect
Using Bypasses
Driver
Polysilicon word line
Polysilicon word line
Metal word line
Metal bypass
Driving a word line from both sides
Using a metal bypass
WL
WL K cells
2nd
Interconnect
Reducing RC-delay
Repeater
(chapter 5)
2nd
Interconnect
Repeater Insertion (Revisited)
Taking the repeater loading into account
For a given technology and a given interconnect layer, there exists
an optimal length of the wire segments between repeaters. The
delay of these wire segments is independent of the routing layer!
2nd
Interconnect
INTERCONNECT
2nd
Interconnect
L di/dt
Impact of inductance on supply
voltages:
Change in current induces a
change in voltage
Longer supply lines have larger L
C
L
V
DD
V
DD
L
i ( t )
V
out V
in
GND
L
2nd
Interconnect
L di/dt: Simulation
0 0.5 1 1.5 2
x 10
-9
0
0.5
1
1.5
2
2.5
V
o
u
t

(
V
)

0 0.5 1 1.5 2
x 10
-9
0
0.02
0.04
i
L

(
A
)

0 0.5 1 1.5 2
x 10
-9
0
0.5
1
V
L

(
V
)

time (nsec)
0 0.5 1 1.5 2
x 10
-9
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2
x 10
-9
0
0.02
0.04
0 0.5 1 1.5 2
x 10
-9
0
0.5
1
time (nsec)
Input rise/fall time: 50 psec Input rise/fall time: 800 psec
decoupled
Without inductors
With inductors
2nd
Interconnect
Dealing with Ldi/dt
Separate power pins for I/O pads and chip core.
Multiple power and ground pins.
Careful selection of the positions of the power
and ground pins on the package.
Increase the rise and fall times of the off-chip
signals to the maximum extent allowable.
Schedule current-consuming transitions.
Use advanced packaging technologies.
Add decoupling capacitances on the board.
Add decoupling capacitances on the chip.
2nd
Interconnect
Choosing the Right Pin
Chip
L
L
Bonding wire
Mounting
cavity
Lead
frame
Pin
2nd
Interconnect
Decoupling Capacitors
SUPPLY
Board
wiring
Bonding
wire
Decoupling
capacitor
CHIP
C
d
1
2
Decoupling capacitors are added:
on the board (right under the supply pins)
on the chip (under the supply straps, near large buffers)
2nd
Interconnect
De-coupling Capacitor Ratios
EV4
total effective switching capacitance = 12.5nF
128nF of de-coupling capacitance
de-coupling/switching capacitance ~ 10x
EV5
13.9nF of switching capacitance
160nF of de-coupling capacitance
EV6
34nF of effective switching capacitance
320nF of de-coupling capacitance -- not enough!
Source: B. Herrick (Compaq)
2nd
Interconnect
EV6 De-coupling Capacitance
Design for AIdd= 25 A @ Vdd = 2.2 V, f = 600
MHz
0.32-F of on-chip de-coupling capacitance was
added
Under major busses and around major gridded clock drivers
Occupies 15-20% of die area
1-F 2-cm
2
Wirebond Attached Chip Capacitor
(WACC) significantly increases Near-Chip de-
coupling
160 Vdd/Vss bondwire pairs on the WACC minimize
inductance
2nd
Interconnect
EV6 WACC
587 IPGA
Microprocessor
WACC
Heat Slug
389 Signal - 198 VDD/VSS Pins
389 Signal Bondwires
395 VDD/VSS Bondwires
320 VDD/VSS Bondwires
2nd
Interconnect
The Transmission Line
The Wave Equation
V
in
V
out
r
g c
r r
x
g c
r
g c g c
l l l l
2nd
Interconnect
Design Rules of Thumb
Transmission line effects should be considered when the
rise or fall time of the input signal (t
r
, t
f
) is smaller than the
time-of-flight of the transmission line (t
flight
).
t
r
(t
f
) << 2.5 t
flight
Transmission line effects should only be considered when
the total resistance of the wire is limited:
R < 5 Z
0
The transmission line is considered lossless when the total
resistance is substantially smaller than the characteristic
impedance,
R < Z
0
/2
2nd
Interconnect
Should we be worried?
Transmission line effects
cause overshooting and non-
monotonic behavior
Clock signals in 400 MHz IBM Microprocessor
(measured using e-beam prober) [Restle98]
2nd
Interconnect
Matched Termination
Z
0
Z
L
Z
0
Series Source Termination
Z
0
Z
0
Z
S
Parallel Destination Termination
2nd
Interconnect
Segmented Matched Line Driver
Z
0
c
1
c
2
s
0
s
1
s
2
s
n
c
n
Z
L
GND
VDD
In
2nd
Interconnect
Parallel Termination
Transistors as Resistors
0.5
Normalized Resistance (
V
)
1
PMOS with-1V bias
NMOS-PMOS
PMOS only
NMOS only
1.5
V
R
(Volt)
2 2.5 0
1.1
1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
Out
M
r
V
dd
Out
M
r
V
dd
V
bb
Out
M
rp
M
rn
V
dd
2nd
Interconnect
Output Driver with Varying
Terminations
V
out
(V)
V
out
(V)
1 2 3 4
time (sec)
Revised design with matched driver impedance
V
s
V
d
V
in
5 6 7 8 0
1
0
1
2
3
4
1 2 3 4
Initial design
V
s
V
d
V
in
5 6 7 8 0
1
0
1
2
3
4
V
in
L = 2.5 nH
V
DD
V
s
V
d
V
DD
Clamping
Diodes
C
L
= 5 pF C
L
L = 2.5 nH
L =
2.5 nH Z
0
=
50 O
275
120
2nd
Interconnect
The Network-on-a-Chip
Embedded
Processors
Memory
Sub-system
Accelators
Configurable
Accelerators
Peripherals
Interconnect Backplane

Digital Integrated Circuits: A Design Perspective

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