Gii thiu Vi iu khin AT89C51

Mc tiu

H tr k thut cho sinh vin yu thch lnh vc thit k Robot v cc ng dng trong iu khin t ng.

>Ni dung>

Ni dung

Gii thiu mt s h vi iu khin MCS51, PIC, AVR v s la chn AT89C51.

Yu cu v Kin thc nn.

Cu trc bn ngoi: Thng s k thut, s chn IC v chc nng ca cc chn.

T chc bn trong AT89C51: Cc thanh ghi, b nh chng trnh - Flash ROM, cc port vo ra, RAM, b phn timer v cc ngt (Port ni tip, Timer).
Hng dn thit k phn cng, mt s im cn ch . Sinh vin t cu hi.
>Mt s h VK>

Gii thiu mt s h Vi iu khin

Vi iu khin h PIC: PIC16F83, PIC16F84, PIC16CR83, PIC16CR84, RISC

Vi iu khin h AVR: ATMEGA8, ATMEGA16, ATMEGA32, ATMEGA64, AT90S2313, RISC Vi iu khin MCS51: AT89C1051, AT89C2051, AT89C4051, AT89C51, AT89C52, AT89C55, CISC
>La chn AT89C51>

S la chn AT89C51

Tnh nng v tc p ng c yu cu k thut trong ng dng khng i hi tc cao (nh x l nh, nhn dng ting ni,). Gi thnh thp hn so vi cc h VK khc. H VK MCS51 c h tr lp trnh iu khin bng c hp ng v C. Cc thit b np Flash ROM c sn ti Khoa.

>Background>

Yu cu v kin thc nn

K thut Vi x l K thut s Linh kin in t.

>Thng s k thut 89C51>

t tnh k thut ca AT89C51

Tng thch vi h MCS-51 4K Bytes Flash ROM. Tn s xung clock hot ng: 0 Hz n 24 MHz H tr bo mt, chng copy chng trnh trong Flash. 128 x 8-bit Internal RAM 32 Programmable I/O Lines (4 Port) Hai Timer/Counters 16-bit. H tr 6 loi ngt: Ngt phn cng, Timer, Serial Port. Mt Port giao tip ni tip. H tr Low-power Idle v Power-down Modes
>Hnh dng>

Cc dng chn ca AT89C51

>Cu trc ngoi>

Cu trc bn ngoi
S chn v ngha cc chn

Port 1 Reset

Port 0
Chc nng khc

Port3 Port 2 Clock

>T chc trong>

Chc nng Port 0

a hp 8 bits a ch thp/D liu khi truy xut CTrnh hoc d liu trong 64K ROM/RAM ngoi. Port 8 bits vo/ra c cc thu h:

- Nhn dng ti a 10mA khi t mc thp.

- Khi c t mc cao, c th s dng nh cc ng vo (Phi s dng in tr ko ln)
Return

Chc nng ca Port 2

Pht ra 8 bits a ch cao khi truy xut CTrnh hoc d liu trong ROM/RAM ngoi. Port vo ra 8 bits:

Nhn dng ti a 10mA khi t mc thp. Khi c t mc cao, c th s dng nh cc ng vo (khng s dng in tr ko ln).
Return

Port 1 v Port 3

Port vo ra 8 bits:

Nhn dng ti a 10mA mc thp.

C th s dng nh cc ng vo khi t mc cao.

Port 3 cn dng phc v cc chc nng c bit ca CPU.

>Next>

Chc nng c bit ca Port 3

P3.0: RXD (serial input port) P3.1: TXD (serial output port) P3.2: INT0 (external interrupt 0) P3.3: INT1 (external interrupt 1) P3.4: T0 (timer 0 external input) P3.5: T1 (timer 1 external input) P3.6: WR (external data memory

write strobe) P3.7: RD (external data memory read strobe)

Return

Cc chc nng khc

VCC
2

U1
39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 9 19 18 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST XTAL1 XTAL2 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INTO P3.3/INT1 P3.4/TO P3.5/T1 P3.6/WR P3.7/RD PSEN ALE/PROG EA/VPP 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 29 30 31

SW1
1

10uF

Reset nu RST c gi mc cao tgian 24TCK

8.2K

VCC

1K

CRYSTAL

Chu k: TCK
33pF

AT89C51

33pF

EA: External Access Enable VPP: 12V khi lp trnh Flash

>>Next>>

Cc chc nng khc (tt)

PSEN (Program Store Enable) dng cho php truy xut b nh chng trnh ngoi. ALE (Address Latch Enable):

Cht 8 bits a ch1 thp khi 6 truy xut chng trnh ngoi. Pht ra tn hiu c f = f CLOCK6

PROG (program pulse input): Xung np chng trnh cho Flash

Return

T chc bn trong
INT0 INT1
256 Bytes RAM

Interrupt Control

4KB Flash ROM

SFRs 128Byte cao Timer0 RAM 128Byte thp Timer1

Counter Inputs ACC B PC

CPU
Bus Control I/O Ports Serial Port TXD RXD
P0 P2 P1 P3

OSC

>Hng dn thit k>

SFRs: Special Function Registers

Cc thanh ghi SFRs c a ch t 80H n FFH
98 9F 9E 9D 9C 9B 9A 99 98 SCON FF F0 90 97 96 95 94 93 92 91 90 P1 E0 8D not bit addressable TH1 8C not bit addressable TH0 D0 8B not bit addressable TL1 8A not bit addressable TL0 B8 89 not bit addressable TMOD 88 8F 8E 8D 8C 8B 8A 89 88 TCON B0 87 not bit addressable PCON A8 83 not bit addressable DPH 82 not bit addressable DPL A0 81 not bit addressable SP 80 87 86 85 84 83 82 81 80 P0 99
Return

F7 F6 F5 F4 F3 F2 F1 F0

E7 E6 E5 E4 E3 E2 E1 E0 ACC D7 D6 D5 D4 D3 D2 - D0 PSW - BC BB BA B9 B8 IP

B7 B6 B5 B4 B3 B2 B1 B0 P3 AF - - AC AB AA A9 A8 IE

A7 A6 A5 A4 A3 A2 A1 A0 P2 not bit addressable SBUF

PSW: Program Status Word

Thanh ghi t trng thi a ch V tr Tn bit D7 CY D6 AC D5 F0 D4 D3 D2 D1 D0 P
PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0

RS1 RS0 OV

Auxiliary flag Carry flag

Return

Parity flag Overflow flag Register Bank Select 00: Bank 0 01: Bank 1 10: Bank 2 11: Bank 3

IP: Interrupt Priority Register

Thanh ghi u tin ngt (Cc bit tc ng cao) a ch BF BE BD BC BB BA B9 B8 V tr IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 Tn bit PS PT1 PX1 PT0 PX0
1BH 13H 0BH 03H ch: 23H

1: High Priority 0: Low Priority

Serial interface

Timer 1 External interrupt 1 Timer 0 External interrupt 0

Th t u tin

Return

IE: Interrupt Enable Register

Thanh ghi ngt (Cc bit tc ng cao) a ch AF AE V tr IE.7 Tn bit EA EA: Cho php ngt 1: Cho php 0: Cm tt c ngt
Enable/Disable serial port Enable/Disable Timer1 overflow Enable/Disable external interrupt 1 Enable/Disable Timer0 overflow interrupt Enable/Disable external interrupt 0

AD AC AB AA A9 A8 - IE.4 IE.3 IE.2 IE.1 IE.0 ES ET1 EX1 ET0 EX0

Return

PCON: Power Control Register

Thanh ghi iu khin cng sut

Tn bit SMOD

GF1 GF0 PD IDL

SMOD: Double baud rate Tng tc gp i khi truyn nhn qua cng ni tip

PD (Power down) PD = 1: Oscillator dng CPU ngng hot ng

IDL (Idle) IDL = 1: CPU ngng hot ng, ngt CK, cc ngt cn hot ng.

Return

TCON: Timer Control Register

Thanh ghi iu khin Timer (Cc bit tc ng cao) a ch AF8 8E 8D 8C 8B 8A 89 88 V tr TCON.7 TCON.6 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0 Tn bit TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TF1, TF0 (Timer overflow flag) c SET l 1 khi Timer/counter trn. TR1, TR0 (Timer run control bit): Cho php Timer/counter chy. IE1, IE0 (External interrupt edge flag) C ngt, t ng bt ln = 1 khi c ngt tc ng. IT1, IT0 (Interrupt type control) Nu c SET s cho php cc ngt tc ng cnh.

Return

T chc 128 bytes RAM

General Purpose RAM

128 BIT BIT ADDRESSABLE a ch t: 00H n FFH

FF..F8 07..00 REGISTER BANK 3

Khi hot ng, mt Bank s c chn lm cc thanh ghi. Vng nh cn li s c s dng lu tr d liu v lm ngn xp.
REGISTER BANK 0

REGISTER BANK 2 REGISTER BANK 1 R7 R6 R5 R4 R3 R2 R1 R0

7F 30 2F 20 1F 18 17 10 0F 08 07 06 05 04 03 02 01 00

Return

Thit k phn cng

S dng ROM chng trnh ngoi.
A[0..7] A0 A1 A2 A3 A4 A5 A6 A7 U2 2 3 4 5 6 7 8 9 11 1 D1 D2 D3 D4 D5 D6 D7 D8 LE OE 74F573 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 19 18 17 16 15 14 13 12 10 9 8 7 6 5 4 3 25 24 21 23 2 U6 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 A0 A1 A2 A3 A4 A5 A6 A7

ALE

2764 OE CE 22 20

U1
A0 A1 A2 A3 A4 A5 A6 A7 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 9 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST XTAL1 XTAL2 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INTO P3.3/INT1 P3.4/TO P3.5/T1 P3.6/WR P3.7/RD PSEN ALE/PROG EA/VPP 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 29 30 31 VCC 6 4 5 G1 G2A G2B 74LS138 27 1 PGM VPP U5 1 2 3 A B C

VCC
2

SW1
1

10uF

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

15 14 13 12 11 10 9 7

8.2K
CRYSTAL

19 18

ALE

AT89C51 33pF 33pF

>Cch s dng Port>

S dng cc Port
VCC

in tr ko ln

U7 AT89C51 39 38 37 36 35 34 33 32 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 RST EA/VPP P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INTO P3.3/INT1 P3.4/TO P3.5/T1 P3.6/WR P3.7/RD PSEN ALE/PROG 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 29 30 VCC

VCC

10K 220
D1

VCC

220
D1

220
D1

Q1 1

Q1 1

1 2 3 4 5 6 7 8 19 18 9 31

8.2K
3 3

8.2K

>Cc ng dng>

Mt s ng dng

Mch iu khin, nh thi ng m cc thit b gia dng nh n, qut

ng h in t a nng.
Mch n chp vi nhiu hiu ng. Cc thit b tnh gi, thit b vui. Lch vn nin. Cc thit b thng minh.