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16-Bit Increment
incfsz goto incf LO $+2 HI LO LO,W $+2 HI
16-Bit Decrement
decf incfsz goto decf
Comparisons
Enter with value to be tested in W. Exits with Carry set if W is in the range [LOVAL to HIVAL], inclusive. addlw 255-HIVAL addlw (HIVAL-LOVAL)+1
;GRAB X. ;Y >= X? ;IF SO, JUMP AHEAD. ;OTHERWISE, X = X + (Y-X) = Y, ; AND Y = Y - (Y-X) = X.
S5704A Tips & Tricks 1 3
Minimum
Comparisons
Enter with three values stored in registers N1, N2, and N3. Exit with min(N1,N2,N3) in MIN, N1-3 unchanged, W scrambled. movf N1,w subwf N2,W movf skpc movf N1,W N2,W
Reverse 7 Bits
movwf swapf btfsc xorlw btfsc xorlw btfsc xorlw btfsc xorlw btfsc xorlw
Bit-Manipulation
Exits with 0GFEDCBA in W. ;source = 0ABCDEFG. ;W= DEFG0ABC. ;If D = 1, invert D and the 0. ;After this line, W = 0EFGDABC. ;If A = 1, invert ; ;If C = 1, invert ;After this line, bits A and C. A W and C again. = 0EFGDCBA.
Enter with 0ABCDEFG in W. source source,w source,3 0x88 source,6 0x05 source,4 0x05 source,2 0x50 source,0 0x50
Rotate in Place
Bit-Manipulation
Rotate without inserting an extra bit from the carry. Easily extended to multi-bit rotates. Enter with ABCDEFGH in REG. Exits with BCDEFGHA in REG, W scrambled. rlf rlf
q
REG,W REG
Bit-Copy
Copy bits from one register to the same position in another. movf SOURCE,W ;The DEST bits in the positions to ;which were copying must not change ;between this xorwf instruction and ;the xorwf DEST below. ;A "1" in each bit-position were ;copying.. ;this example copies the three LSBs.
xorwf DEST,W
Bit-Manipulation
q
Bit Counter
Count the number of "1" bits in a register. On exit, W contains the number of "1" bits in REG, and REG is scrambled. rrf andlw subwf movf andlw addwf rrf andlw addwf rrf swapf addwf andlw REG,W 0x44 REG REG,W 0x33 REG REG 0x11 REG REG REG,W REG,W 0x0F
S5704A Tips & Tricks 1 7
Bit-Manipulation
q
btfsc BITNUM,0 addwf temp btfsc BITNUM,2 swapf temp movf temp,w
Bit-Manipulation
Set a left-aligned group of bits: clrf reg ;Set bits decfsz reg ;4-7. bcf reg,4 ; incfsz reg ; General method, 2-4 bits set: clrf reg bsf reg,bit1 bsf reg,bit2 bsf reg,bit3 bsf reg,bit4 General method, clrf decfsz bcf bcf bcf 5-7 bits set: reg reg reg,unbit1 reg,unbit2 reg,unbit3
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Set to a power of two: clrf reg bsf reg,bit Set to 255: clrf reg decfsz reg Set a right-aligned group of bits: clrf reg ;Set bits bsf reg,6 ;0-5. decfsz reg ;
q
WAIT
Delays
IF (X == 3) NOP GOTO $+1 ENDIF X = (CYCLES)/4 IF (X) IF (X == 256) X = 0 ENDIF MOVLW ADDLW SKPZ GOTO ENDIF ENDM
S5704A Tips & Tricks 1 10
IF ((CYCLES) > 1027) ERROR "MUST BE <1028 CYCLES!" ENDIF IF ((CYCLES) < 0) ERROR "MUST BE >= 0 CYCLES!" ENDIF X = (CYCLES)%4 IF (X == 1) NOP ENDIF IF (X == 2) GOTO $+1 ENDIF
1999 Microchip Technology Incorporated. All Rights Reserved.
X -1 $-2
Delays
; ; ; ; ;
DELAY 20-271 CYCLES. ENTER WITH NUMBER OF CYCLES TO DELAY IN W. DELAY IS INCLUSIVE OF "MOVLW", CALL, AND RETURN OVERHEAD.
DELAY: MOVWF BTFSC GOTO BTFSS GOTO NOP GOTO COUNTER COUNTER, 0 $+1 COUNTER, 1 SKIP
COUNTER LOOP
Delays
Trading Stack Space for RAM
Delay131072: Delay114688: Delay98304: Delay81920: Delay65536: Delay49152: Delay32768: Delay16384: Delay14336: Delay12288: Delay10240: Delay8192: Delay6144: Delay4096: Delay2048: Delay1792: Delay1536: Delay1280: Delay1024: call call call call call call call call call call call call call call call call call call call Delay16384 Delay16384 Delay16384 Delay16384 Delay16384 Delay16384 Delay16384 Delay2048 Delay2048 Delay2048 Delay2048 Delay2048 Delay2048 Delay2048 Delay256 Delay256 Delay256 Delay256 Delay256 Delay768: Delay512: Delay256: Delay224: Delay192: Delay160: Delay128: Delay96: Delay64: Delay48: Delay32: Delay28: Delay24: Delay20: Delay16: Delay12: Delay8: Delay4: call call call call call call call call call call call call call call call call call return Delay256 Delay256 Delay32 Delay32 Delay32 Delay32 Delay32 Delay32 Delay32 Delay32 Delay4 Delay4 Delay4 Delay4 Delay4 Delay4 Delay4
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Math
q16-Bit
q8-Bit
13
Math
q
;CALCULATE NEW_AVERAGE = (255 * OLD_AVERAGE + NEW_SAMPLE)/256. ;ENTER WITH THE NEW SAMPLE IN W. EXITS WITH THE NEW AVERAGE IN W. AVERAGE: addwf movf skpnc incf subwf skpc decf movf return
;SUM = SUM + SAMPLE. ;(AND WHILE WE'RE HERE, PUT THE OLD ;AVERAGE IN W). ; ;ADJUST THE SUM BY SUBTRACTING THE OLD ;AVERAGE FROM THE NEW SUM. ; ;W=THE NEW AVERAGE (ADJUSTED SUM/256) ;RETURN.
S5704A Tips & Tricks 1 14
Math
qTricks
;Carry-out is only valid if SOURCE<255. ; KZ,W ;valid. 255 ;DEST = DEST + 255 + CARRY. ;DEST = DEST + 0 + CARRY.
DEST
;is valid. ;
{ rlf KZ,W ;DEST = DEST + constant + CARRY, where 15 addlw [constant] ;0 S5704A Tips & Tricks 1 < 255. Carry-out is < constant
Math
qEven
Parity
; Enter with input in register "X". Exits with ; even parity in bits 1, 2, 3, 4, and 5 of ;register "X". ; ; 7 words, 7 cycles. swapf xorwf rrf xorwf rrf rlf xorwf
1999 Microchip Technology Incorporated. All Rights Reserved.
Math
qEven
Parity
;Enter with input in register X. Branches to "ZERO" or "ONE" ;depending on parity. Doesnt modify register X. For odd ;parity, replace "GOTO ZERO" with "GOTO ONE", and vice-versa. ;19 words. 5 or 7 cycles, including branch to ZERO or ONE. SWAPF XORWF ANDLW ADDWF GOTO GOTO GOTO GOTO GOTO GOTO GOTO X,W X,W
00001111B
GOTO GOTO GOTO GOTO GOTO GOTO GOTO GOTO ZERO: .... ONE: ....
S5704A Tips & Tricks 1
17
MPASM Tips
qEQU
vs. #define
equ 5+3 ;MPASM will replace future ;occurrences of "equ1" with the ;value 8. ;MPASM will replace future ;occurrences of "def1" with the ;string"5+3".
equ1
equ
3*equ1 ;This line is equivalent to "x ;equ 3*8", so x = 24. 3*def1 ;THIS line, on the other hand, ;is equivalent to "y equ 3*5+3", ;so y = 18.
S5704A Tips & Tricks 1 18
equ
MPASM Tips
qAccessing
Method #1: REG EQU xxx - 128 .... MOVWF REG Method #2: MOVWF REG
Method #3: MOVWF REG & 0x7F ;Generates no warning, even when ;accidentally used with a ;page-0 register. Method #4: MOVWF REG ^ 0x80 ;Generates no warning when used ;correctly, but does generate a ;warning if accidentally used ;with a page-0 register.
1999 Microchip Technology Incorporated. All Rights Reserved.
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MPASM Tips
qHIGH-and-LOW
vs. Shift-and-AND
BIGNUM
EQU 0x123456 ;LSB will always be set to ;0x56. ;Some versions of MPASM will ;set "MSB" to 0x12; others ;will set it to 0x34.
SAFEMSB EQU (BIGNUM>>16) & 0xFF ;This method will always set ;"SAFEMSB" to 0x12.
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Timing
qExact
; ; ; ;
Enter this section with TMR0 between 128 and 255, inclusive, and the prescaler divide-byratio set to divide-by-4.
; Here, TMRO:PRESCALER can be ; 00:2 or 00:3 or 01:0. BTFSS GOTO TMR0,BIT0 $+1
; TMR0 always increments from 02 to ; 03 right here. When we reload TMR0, ;we need to add 4 to the reload value ;because the MOVLW/MOVWF takes 2 ;cycles and theres an additional 2;cycle synchronization delay. TMR0 ;will resume incrementing at EXACTLY ;the moment when it would have rolled ;over from 03 to 04. MOVLW S5704A Tips & Tricks 1 MOVWF RELOAD+4 TMR0
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Timing
q16-Bit
; Enter with PULSE_WIDTH_HI:LO set to 0000. when PORT,PIN goes low. CHECK_PULSE: INCFSZ DECF BTFSC GOTO DONE: MOVF ADDWF PULSE_WIDTH_LO,W PULSE_WIDTH_HI PULSE_WIDTH_LO PULSE_WIDTH_HI PORT,PIN CHECK_PULSE
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Hardware Interfacing
qZero
Your Master PICmicro controls the Slave PICmicro's MCLR line. The Master normally keeps the Slave's MCLR line high (out of reset). When the Master wants to send a message, it pulls the Slave's MCLR line low, then pulls it high for a short time before pulling it low, then high again. The "message" is the time between MCLR-low pulses.
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qSetting
q4
Hardware Interfacing
Fosc/2, Fosc/8, Fosc/32 and Frc(internal RC) qTad Min. = 1.6 uS for VREF => 3.0V or 3.0uS for VREF < 3.0V For fastest A/D response, calculate the Tad which is closest to the Minimum value for Tad
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Hardware Interfacing
qSetting
qTo
ADCON0: GO/DONE
start an A/D conversion the GO bit should be set to 1. Note: ADON and GO bit should not be set in the same instruction qOn conversion complete, GO/DONE = 0 & ADIF = 1. Fastest check of A/D conversion completion: Bit test ADIF or the GO/DONE bit in tight loop . btfsc goto ADCON0,DONE $-1
A/D completion using Interrupts takes: 3T cycles for interrupt latency 10T cycles for Context Saving + 1T cycle for ADIF check Total = 14 T cycles
S5704A Tips & Tricks 1 25
Hardware Interfacing
qA/D
Conversion in Sleep
digital noise during A/D conversion. qEnable Frc mode for Tad qEnable or disable A/D Interrupt qStart A/D conversion and goto sleep
qReduces
qOn
A/D Completion: qIf interrupt is enabled then CPU wakes up from sleep qIf interrupt is disabled then CPU does not wake up from sleep, but A/D circuit is turned OFF (ADON is still set).
Crystal mode conversion in sleep is slow since most crystals take 2 mS or more to wake-up
qFor
qIn
Miscellaneous
qDirect
TBL: MACRO LOCAL ADDWF ADDLW ADDLW ADDLW ADDLW ADDLW ADDLW ADDLW ADDLW
X:
IF ((HIGH $) != (HIGH X)) ERROR "TABLE CROSSES PAGE ERROR BOUNDARIES! DO ERROR SOMETHING! ENDIF ENDM
1999 Microchip Technology Incorporated. All Rights Reserved.
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q"Switch"
Statement
VAL1 CASE1
Miscellaneous
;IF W = VAL1, GOTO CASE1. ; ;IF W = VAL2, GOTO CASE2. ; ;IF W = VAL3, GOTO CASE3. ; ;IF W = VAL4, GOTO CASE4. ;
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Resources
q
q q q
PICLIST Archives
http://anick.simplenet.com/piclist/