To provide applications with the illusion of having a very large amount of memory, a technique known as virtual memory was

developed. In a virtual memory system, not all parts of a process are stored in the main memory. The seldom-used parts of a program are stored elsewhere, such as in disks and other storage devices, and are only placed in the main memory when needed.

 Memory management is the general term to cover all techniques of translating a virtual address to physical address. The special hardware used to do the translation is the memory management unit (MMU) via the use of page tables PTs. The MMU receives the virtual address generated by the CPU and converts it to the corresponding physical address, which can be used to access the main memory.

 Each virtual memory reference can cause two physical memory accesses
One to fetch the page table One to fetch the data

To overcome this problem a high-speed cache is set up for page table entries called a Translation Lookaside Buffer (TLB)
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 processors include a translation lookaside buffer (TLB) that speeds up address translation.
TLB contains page table entries (PTEs) of recently used virtual-to physical address translations.

 Given a virtual address, processor examines the TLB. If page table entry is present (TLB hit), the frame number is collected and the physical address is formed. If page table entry is not found in the TLB (TLB miss), the page number is used to address the page table.

 The aim of this study is to design and implement a TLB design structures using VHDL. fully associative structures consume the least amount of power and provide the shortest fetch time and also produce the lowest miss rate.

CAM: content addressable memory SRAM: static RAM

 the previous simplified block diagram of the TLB. It is mainly composed of the content addressable memory (CAM), which stores the VPN of available translations, and the static random access memory (SRAM), which stores the corresponding PPN. Content addressable memories (CAMs) differ from ordinary memory in that it allows access through its data rather than by the datas address.

 CAMs are able to support three different operations: (1) write (2) read (3) match. The write and read operations access the CAM as an ordinary memory block, where a write or read is done from a specified memory location.

 The match operation looks for a match between the input data and data stored in the memory array.

Each of the stored word has its corresponding match flag indicating a match between the data and the corresponding word, and signaling the corresponding word in the SRAM to output its data.

State machine of the MMU

The system is represented by 5 states: 0- Idle state 1- Read state 2- Hit state 3- Miss state 4- Page Fault state

State machine of the MMU

Idle state MMU is waiting for a read signal from cpu Read state read virtual address from TLB Hit state get Physical address from TLB and send out to read from RAM. Miss state read virtual address from Page table (PT) and send out to read from RAM. PAGE FAULT virtual address doesnt exist in page table and system will have to get it from auxiliary memory.

State machine of the MMU