MEMORY MANAGEMENT UNIT

PRESENTED BY RESMI.K.G Roll No:17

MEMORY SYSTEM
ARM processors are used in embedded systems
Different types of memory

Multiple types 2. Catches 3. Write buffers 4. Virtual memory and other remapping techniques
1.

MMU ARCHITECTURE
VIRTUAL TO PHYSICAL ADRESS MAPPING Address generated by the ARM processor is called a virtual adress
MMU allows this address to be mapped to a different

physical address

MEMORY ACCESS PERMISSIONS

These control whether a program has no access,read

only access to the memory area

When an access is not permitted a memory abort is

signaled to the ARM processor

SYSTEM CONTROL COPROCESSOR

They allow high level control of the system
They are also used to provide status information about

memory aborts The process of doing full translational table lookup is called translation table walk

MEMORY ACCESS SEQUENCE

When the ARM generates a memory access MMU first

looks up the virtual address of the access in the TLB If the implementation has separate data and instruction TLBs,it uses The instruction TLB for an instruction fetch The data TLB for all other types of access

CACHED MMU MEMORY SYSTEM

ENABLING AND DISABLING

MMU can be enabled and disabled by writing bit[0]

register 1 of the system coprocessor When MMU is disabled,memory access is treated as follows The values of C and B bits are irrelevant The data access is treated as uncachable and unbufferable

TRANSLATION PROCESS

The MMU supports memory accesses based on sections or pages The different page sizes are supported 1. Tiny pages 2. Small pages 3. Large pages

TRANSLATION TABLE
It is held in main memory has 2 levels

1.First level table It holds section translations and pointers to second level tables 2.Second level table It holds both large and small page translations

DOMAINS

A domain is a collection of sections,large pages and small pages Two kinds of domain access are supported 1.Clients 2.Managers

ABORTS
MMU fault

The MMU detects the restriction and signals the processor External abort The external memory system signals on illegal memory access

FAR AND FSR

The FAR is updated with a 4-bit fault status and the

domain number of the access The virtual address which caused the data abort is written into FAR

EXTERNAL ABORTS
The ARM architecture defines an external abort pin
A line fetch can be safely aborted on any word in the

line transfer Buffered writes cannot be externally aborted The value of a memory location that causes an abort is unpredictable after the abort

CP15 REGISTERS
Register 1 M[bit 0] is the enable/disable bit for the MMU A[bit 1] enables and disables allignment fault checking S[bit 8] is the system protection bit R[bit 9] is the ROM protection bit

REGISTER 2
Reading from register 2 returns the physical adress Writing to register 2 updates the physical adress

REGISTER 3

REGISTER 5

REGISTER 6

REGISTER 8 AND 10
Register 8 is a write only register which is used to

control TLBS Register 10 is used for TLB lockdown TLB lockdown is a feature of ARM memory systems

CONCLUSION
MMU is a sophisticated system to control virtual to

physical address mapping.

MMU architecture allows fine grained control of

memory.
It also perfoms access to memory and other memory

attributes

REFERENCE
[1].Arm reference manual

[2].www.arm.com

[3].www.wikipedia.com

THANK YOU