MAR(Memory address register): It holds the address of the byte or word to be fetched from the external memories.

Processor issues the address of instructions or data to MAR before it initiates fetch cycle MDR(Memory data register): It holds a byte or word fetched(or to be sent) from(to) external memory or IO address.

System buses: Internal buses: it internally connects all the structural units inside the processor. Its width can be 8,16,32,48 or 64 bits. Address bus: An external bus that carries address from MAR to memory as well as IO devices and other units of a system. Data bus: An external bus that carries, during a read or write operation, the bytes for instruction or data from or to an address. The address is determined by the MAR.

Control bus: An external set signals to carry control signals to processor or a memory or a device. BIU: An interface between processors internal units and external buses. IR(Instruction register): It sequentially takes instruction codes(op code) to execution unit of a processor. ID(Instruction decoder): It decodes the instruction received at the IR and passes it to processor CU.

CU(Control unit): it controls all the bus activities and unit functions needed for processing. ARS(Application register set): (a) A set of on-chip registers used during processing of instruction of an application program or (b) a register window, (c) a subset of registers with each subset storing static variables of a software-routine or a (d) a register file associated to a unit such as ALU or FLPU.

PC(Program counter): It generates an instruction cycle by sending the address defined by it to memory through MAR. It auto-increments as the instructions are fetched regularly and sequentially.It is called instruction pointer in 80*86 processor. SP(Stack pointer): A pointer for an address, which corresponds to stack-top in memory.

Caches: Instruction, Data and Branch Target Caches and associated PFCU (Pre-fetch control unit) for prefetching the instructions, data and next branch target instructions, respectively. Multi-way Cache Example- 16 kB, 32-way Instruction cache with 32 byte block for data and 16 kB in ARM. Cache block Enables simultaneous caching of several memory locations of a set of instructions.

AOU (Atomic Operations Unit ) An instruction is broken into number of processor instructions called atomic operations (AOs), AOU finishes the AOs before an interrupt of the process occurs Prevents problems arising out of incomplete processor operations on the shared data in the programs

Fixed Instruction Cycle Time RISC processor core 32-bit Internal Bus Width to facilitate the availability of arithmetic operations on 32- bit operands in a single cycle. The 32-bit bus a necessity for signal processing and control system instructions. Program-Counter (PC) bits and its reset value Stack-Pointer bits with and its initial reset value

Instruction, Branch Target and Data Cache Memory-Management unit (MMU) Floating Point Processing unit System Register Set Floating Point Register Set Pre-fetch Control Unit for data into the I- and Dcaches Instruction level parallelism units (i) multistage pipeline (ii) Multi-line superscalar processing

Executing most instructions on in a single clock cycle execution per instruction (by hardwired implementation of instructions) Using multiple register-sets or register windows or files and Greatly reducing ALU dependency on the external memory accesses for data due to the reduced number of addressing modes provided for the ALU instructions.

Before, ALU operations, the operands are loaded into the registers and similarly the write back result is in the register and then stored at the external memory addresses.

In cycle 1, the first instruction I1 enters the instruction fetch (IF) stage of the pipeline and stops at pipeline latch (buffer) between instruction fetch and instruction decode (ID) stage of the pipeline. In cycle 2, the second instruction I2 enters the instruction fetch stage, while instruction I1 proceeds to instruction decode stage. In cycle 3 the instruction I1 enters the register (inputs) read (RR) stage, instruction I2 is in the instruction decode stage, and instruction I3 enters instruction fetch stage.

In cycle 4 I1 moves to the execute stage and in 5th cycle to result write back stage.