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3.1. Gii thiu VHDL 3.2. Cu trc m lnh 3.3. Cc kiu d liu 3.4. Cc php ton v thuc tnh
CE=1
CE=0
Count=3 CE=1
Count=2
CE=0
Count=2
1. Ta ang trng thi Count=0 2. CE = 0: i chn ca sn ln ca xung nhp 3. CE=1: i chn ca 1 sn ln khc nhng cha m 4. Sn ln ca xung nhp: chuyn sang trng thi Count=1, CE vn =1 5. CE = 0: i chn ca 1 sn ln khc 6. Sn ln ca xung nhp: chyn sang Count=1, vi CE=0
Q1Q0=10
CE=1
Q1Q0=10 CE=0
CE=1
Q0 Q1n=D1 Q1 0 0 1 CE 0 1 0 1 1 CE Q0n=D0
Q0 Q1 0 1 1 0 1 0 0 1
D to be applied is identical to Qn
D1
Q1
Q Q0 Q
Q0n
D0
10
Q
Q0 Q
Q0n
D0
Clk
CE
Q1
11
Q0
CE=0 Count=0 Y=0 CE=1 CE=0 Count=3 Y=1 CE=1 Count=1 Y=0 CE=1 Count=2 Y=0
CE=0
CE=0
CE=1
12
13
CE=0 Q1Q0=00 Y=0 CE=1 CE=0 Q1Q0=11 Y=1 CE=1 Q1Q0=01 Y=0 CE=1 Q1Q0=10 Y=0
CE=0
CE=0
CE=1
14
15
CE=0 CE=1
Q1Q0=01 Y=0
CE=1 CE=0
Q1Q0=11 Y=1
CE=1
Q1Q0=10 Y=0
CE=0
CE=1
16
Outputs Y 0 0 0 1
Q0 Q1n=D1 Q1 0 0 1 CE 0 1 0 Y Q1 1 1 Q0 0 0 0 1 CE Q0n=D0
Q0 Q1 0 1 1 0 1 0 0 1
17
D to be applied is identical to Qn
CE Q1 Q0 Q1n
D1
Q1
Q Q0 Q
Q0n
D0
18
Q
Q0 Q
Q0n
D0
Clk CE Q1 Q0
19
CE=0/Y=0
21
23
CE=0/Y=0 CE=1/Y=0
Q1Q0=01
CE=1/Y=0
Q1Q0=10 CE=0/Y=0
CE=1/Y=0
24
Next state/Outputs Q1nQ0n/Y CE=0 CE=1 00/0 01/0 01/0 10/0 10/0 11/0 11/0 00/1
Next state/Outputs Q1nQ0n/Y CE=0 CE=1 00/0 01/0 01/0 10/0 10/0 11/0 11/0 00/1 Q0
Q0
Q1n=D1
Q1
0 0 1 1
Q0n=D0
Q1
0 1 1 0
CE Y
0 1 0 1 Q0
Q1 0 0 0 0 0 0 0 1
CE
1 0 0 1
25
D to be applied is identical to Qn
CE
CE Q1 Q0 Q1n
D1
Q1
Q Q0 Q
Q0n
D0
26
Q1n
D1
Q1
Q
Q0 Q
Q0n
D0
Clk CE Q1 Q0
27
S*=F(S,I)
Clk
28
Clk
29
Logic t hp
V 1 u ra: Pr_state
Cha cc trigger
reset
Logic t hp
Nx_state
Hot ng ca mch
- Khi reset th Pr_state tr v trng thi khi to ca h thng. - Ngc li, khi c clock khi tun t s lu tr trng thi Nx_state v chuyn ti u ra trng thi Pr_state
Logic tun t
clock reset
Logic tun t
clock
reset
END PROCESS
Input
Output
Logic t hp
Pr_state
Nx_state
WHEN five => count <= 0101; next_state <= six; WHEN six => count <= 0110; next_state <= seven; WHEN seven => count <= 0111; next_state <= eight; WHEN eight => count <= 1000; next_state <= nine; WHEN nine => count <= 1001; next_state <= zero; END state_machine;
H c hai trng thi l STATE0 v STATE1 u ra x = a khi h trng thi STATE0 u ra x = b khi h trng thi STATE1 d = 0 h gi nguyn trng thi d = 1 h chuyn trng thi
FSM
x
x=a x=b
rst